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參數(shù)資料
型號: LTC1564CG#TR
廠商: Linear Technology
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC ANTIALIASING FILTER 16-SSOP
標(biāo)準(zhǔn)包裝: 2,000
濾波器類型: 抗混迭
頻率 - 截止或中心: 150kHz
濾波器數(shù): 1
濾波器階數(shù): 8th
電源電壓: 2.7 V ~ 10.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
其它名稱: LTC1564CGTR
7
LTC1564
1564fa
AGND (Pin 15): Analog Ground. The AGND pin is at the
midpoint of an internal resistive voltage divider, develop-
ing a potential halfway between the V+ and Vpins, with
an equivalent series resistance to the pin of nominally 7k.
(In the shutdown state, analog switch FETs interrupt the
voltage-divider resistors and the AGND pin assumes a
high impedance.) AGND also serves as the internal half-
supply reference in the LTC1564, tied to the noninverting
inputs of all internal op amps and establishing the ground
reference voltage for the IN and OUT pins. Because of this,
very “clean” grounding is recommended, including an
UU
U
PI FU CTIO S
LTC1564
DIGITAL GROUND PLANE
(IF ANY)
ANALOG
GROUND PLANE
1
SINGLE-POINT
SYSTEM GROUND
23
4
5
6
7
1564 F01
8
16
15
14
13
12
11
0.1
F
V+
10
9
0.1
F
V
Figure 1. Dual Supply Ground Plane Connection
LTC1564
DIGITAL GROUND PLANE
(IF ANY)
ANALOG
GROUND PLANE
1
SINGLE-POINT
SYSTEM GROUND
23
4
5
6
7
1564 F01
8
16
V+/2
REFERENCE
15
14
13
12
11
0.1
F
1
F
V+
10
9
Figure 2. Single Supply Ground Plane Connection
analog ground plane surrounding the package. For dual
supply operation, this ground plane will be tied to the 0V
point and the AGND pin should connect directly to the
ground plane (Figure 1). For single supply operation, in
contrast, if the system signal ground is at V, the ground
plane should tie to Vand the AGND pin should be AC-
bypassed to the ground plane by at least a 0.1
F high
quality capacitor (at least 1
F for best AC performance)
(Figure 2). As with all high dynamic range analog circuits,
performance in an application will reflect the quality of the
grounding.
Table 3. Summary of LTC1564 Digital Controls and Modes
EN
RST
CS/HOLD
F3
F2
F1
F0
G3
G2 G1
G0
FUNCTION
1
XXXX
XX
X
Shutdown Mode. Filter Disabled. Latch Holds F and G Inputs Present
when Last CS/HOLD = 0
1
0
XXXX
XX
X
Shutdown Mode. Filter Disabled. Latch Accepts F and G Inputs
1
0
X
XXXX
XX
X
Shutdown Mode. Filter Disabled. Latch Contents (F and G) Reset to All Zeros
0
1
0
0000
X
Mute Mode. Filter Active, Zero Gain, Reduced Noise
0
X
XXXX
XX
X
Mute Mode. Filter Active, Zero Gain, Reduced Noise. Latch Contents
(F and G) Reset to All Zeros
0
1
Other Than 0000
X
Normal Filtering Operation. Latch Holds F and G Inputs Present
when Last CS/HOLD = 0
0
1
0
Other Than 0000
X
Normal Filtering Operation. Filter Responds Directly to F and G Input
Pins (See Separate Pin Descriptions)
X = Doesn’t Matter
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