參數(shù)資料
型號: LTC1522
廠商: Linear Technology Corporation
英文描述: Micropower, Regulated 5V Charge Pump DC/DC Converter
中文描述: 微功耗,電壓5V充電泵DC / DC轉(zhuǎn)換器
文件頁數(shù): 6/8頁
文件大?。?/td> 223K
代理商: LTC1522
6
LTC1522
APPLICATIO
S I
N
FOR
ATIO
U
W
U
Figure 2. Ultralow Quiescent Current (<2.1
μ
A) Regulated Supply
1
2
3
4
8
7
6
5
NC
SHDN
GND
C
NC
V
IN
V
OUT
C
+
LTC1522
FROM MPU
10
μ
F
10
μ
F
V
OUT
5V
4%
SHDN PIN WAVEFORMS:
LOW I
Q
MODE (2Hz TO 100Hz, 95% TO 98% DUTY CYCLE)
I
OUT
100
μ
A
V
OUT
LOAD ENABLE MODE
(I
OUT
= 100
μ
A TO 20mA)
0.22
μ
F
V
2.7V TO 5V
+
+
1522 F02
INPUT VOLTAGE (V)
0.0
2.0
4.0
6.0
S
μ
A
5.0
1522 F03a
2.0
3.0
4.0
Figure 3a. No-Load I
CC
vs Input Voltage for Circuit in Figure 3
OUTPUT CURRENT (
μ
A)
1
10
100
1000
M
1000
1522 F03b
1
10
100
SHDN ON PULSE WIDTH = 200
μ
s
C
OUT
= 10
μ
F
The LTC1522 must be out of shutdown for a minimum
duration of 200
μ
s to allow enough time to sense the output
and keep it in regulation. A 2Hz, 98% duty cycle signal will
keep V
OUT
in regulation under no-load conditions. As the
V
OUT
load current increases, the frequency with which the
part is taken out of shutdown must also be increased to
prevent V
OUT
from drooping below 4.8V during the OFF
phase (see Figure 3b). A 100Hz 98% duty cycle signal on
the SHDN pin ensures proper regulation with load currents
as high as 100
μ
A. When load current greater than 100
μ
A
is needed, the SHDN pin must be forced low as in normal
operation. The typical no-load supply current for this
circuit with V
IN
= 3V is only
2.1
μ
A
.
Each time the LTC1522 comes out of shutdown, the part
delivers a minimum of one clock cycle worth of charge to
the output. Under high V
IN
(>3.3V) and/or low I
OUT
(<10
μ
A)
conditions, this behavior may cause a net excess of charge
to be delivered to the output capacitor if a high frequency
signal is used on the SHDN pin (e.g., 50Hz to 100Hz).
Under such conditions, V
OUT
will slowly drift positive and
may even go out of regulation. To avoid this potential
problem in the low I
Q
mode, it is necessary to switch the
part in and out of shutdown at the minimum allowable
frequency (refer to Figure 3b) for a given output load.
Figure 3b. Maximum SHDN OFF Time vs Output Load Current
for Ultralow I
Q
Operation
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