參數(shù)資料
型號: LTC1503IS8-1.8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: High Efficiency Inductorless Step-Down DC/DC Converters
中文描述: 1-OUTPUT DC-DC REG PWR SUPPLY MODULE
封裝: 0.150 INCH, PLASTIC, SOP-8
文件頁數(shù): 8/12頁
文件大?。?/td> 187K
代理商: LTC1503IS8-1.8
8
LTC1503-1.8/LTC1503-2
2ms/DIV
1503-1.8/2 F02b
LTC1503-2
C
SS
= 0nF
C
OUT
= 10
μ
F
R
LOAD
= 50
Capacitor Selection
For best performance, it is recommended that low ESR
capacitors be used for C
IN
and C
OUT
to reduce noise and
ripple. If the ESR of the output capacitor is too high
(>0.5
), both efficiency and output load regulation may
be degraded. The C
IN
and C
OUT
capacitors should be either
ceramic or tantalum and should be 10
μ
F or greater. If the
input source impedance is very low (<0.5
), C
IN
may not
be needed. Ceramic capacitors are recommended for the
flying caps C1 and C2 with values of 0.47
μ
F to 2.2
μ
F.
Smaller values may be used in low output current applica-
tions (e.g., I
OUT
< 10mA). For best performance choose
the same capacitance value for both C1 and C2.
Output Ripple
Normal LTC1503-X operation produces voltage ripple on
the V
OUT
pin. Output voltage ripple is required for the parts
to regulate. Low frequency ripple exists due to the hyster-
esis in the sense comparator and propagation delays in the
charge pump enable/disable circuits. High frequency ripple
is also present mainly from the ESR (equivalent series
resistance) in the output capacitor. Typical output ripple
(V
IN
= 3.6V) under maximum load is 25mV peak-to-peak
with a low ESR 10
μ
F output capacitor.
The magnitude of ripple voltage depends on several fac-
tors. High input voltages increase the output ripple since
more charge is delivered to C
OUT
per charging cycle. Large
output current load and/or a small output capacitor (<10
μ
F)
results in higher ripple due to higher output voltage dV/dt.
High ESR capacitors (ESR > 0.5
) on the output pin cause
high frequency voltage spikes on V
OUT
with every clock
cycle.
There are several ways to reduce the output voltage ripple
(see Figure 3). A larger C
OUT
capacitor (22
μ
F or greater)
will reduce both the low and high frequency ripple due to
the lower C
OUT
charging and discharging dV/dt and the
lower ESR typically found with higher value (larger case
size) capacitors. A low ESR ceramic output capacitor will
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen. A reasonable compromise is to use a 10
μ
F to 22
μ
F
tantalum capacitor in parallel with a 1
μ
F to 3.3
μ
F ceramic
approximately 1.9V. Since the ramp rate on the SHDN/SS
pin controls the ramp rate on V
OUT
, the average inrush
current can be controlled through selection of C
SS
and
C
OUT
. For example, a 4.7nF capacitor on SHDN/SS results
in a 4ms ramp time from 0.35V to 1.9V on the pin. If C
OUT
is 10
μ
F, the 4ms V
REF
ramp time results in an average
C
OUT
charge current of only 5mA (see Figure 2c).
5
1
R
LOAD
C
SS
1503-1.8/2 F02a
V
CTRL
ON OFF
SHDN/SS
V
OUT
LTC1503-X
(a)
V
2V/DIV
V
1V/DIV
(b)
2ms/DIV
1503-1.8/2 F02b
LTC1503-2
C
SS
= 4.7nF
C
OUT
= 10
μ
F
R
LOAD
= 50
V
2V/DIV
V
1V/DIV
(c)
Figure 2. Shutdown/Soft-Start Operation
APPLICATIOU
W
U
U
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