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參數(shù)資料
| 型號： | LTC1458LISW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R 3V QUAD 28SOIC |
| 標準包裝： | 1,000 |
| 設置時間： | 14µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.4mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
8
LTC1458/LTC1458L
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 48-bit
word, DAC A first, then DAC B, DAC C and DAC D. The MSB
is loaded first for each DAC. The DAC registers load the
data from the shift register when CS/LD is pulled high. The
CLK is disabled internally when CS/LD is high. Note: CLK
must be low before CS/LD is pulled low to avoid an extra
internal clock pulse.
The buffered output of the 48-bit shift register is available
on the DOUT pin which swings from ground to VCC.
Multiple LTC1458/LTC1458Ls may be daisy-chained to-
gether by connecting the DOUT pin to the DIN pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
Reference
The LTC1458L has an internal reference of 1.22V with a full
scale of 2.5V (gain of 2 configuration). The LTC1458
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than VCC/2 and be
capable of driving the 15k minimum DAC resistor ladder.
The external reference must always be less than
VCC – 1.5V. The reference output voltage noise spectral
density at 1kHz is 300nV/
√Hz.
Voltage Output
The rail-to-rail buffered output of the LTC1458 family can
source or sink 5mA when operating with a 5V supply over
the entire operating temperature range while pulling to
within 300mV of the positive supply voltage or ground.
The output swings to within a few millivolts of either
supply rail when unloaded and has an equivalent output
resistance of 40
when driving a load to the rails. The
output can drive 1000pF without going into oscillation.
The output voltage noise spectral density at 1kHz is
600nV/
√Hz.
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal 1LSB change
between any two adjacent codes. The DNL error between
any two codes is calculated as follows:
DNL
= (
VOUT – LSB)/LSB
VOUT = The measured voltage difference between
two adjacent codes
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
DEFI ITIO S
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OPERATIO
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