8
LTC1454/LTC1454L
OPERATIO
U
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. Data is loaded as one 24-bit
word, DAC A first, then DAC B. The MSB is loaded first for
each DAC. The DAC registers load the data from the shift
register when CS/LD is pulled high. The CLK is disabled
internally when CS/LD is high. Note: CLK must be low
before CS/LD is pulled low to avoid an extra internal clock
pulse.
The buffered output of the 24-bit shift register is available
on the DOUT pin which swings from ground to VCC.
Multiple LTC1454/LTC1454Ls may be daisy-chained to-
gether by connecting the DOUT pin to the DIN pin of the next
chip, while the CLK and CS/LD signals remain common to
all chips in the daisy-chain. The serial data is clocked to all
of the chips, then the CS/LD signal is pulled high to update
all of them simultaneously.
Reference
The LTC1454L has an internal reference of 1.22V with a full
scale of 2.5V (gain of 2 configuration). The LTC1454
includes an internal 2.048V reference, making 1LSB equal
to 1mV (gain of 2 configuration). When the buffer gain is
2, the external reference must be less than VCC/2 and be
capable of driving the 15k minimum DAC resistor ladder.
With a gain of 1 configuration the external reference must
be less than VCC – 1.5V.
Voltage Output
The rail-to-rail buffered output of the LTC1454 family can
source or sink 5mA when operating with a 5V supply while
pulling to within 300mV of the positive supply voltage or
ground. The output swings to within a few millivolts of
either supply rail when unloaded and has an equivalent
output resistance of 40
when driving a load to the rails.
The output can drive 1000pF without going into oscilla-
tion.