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參數(shù)資料
| 型號(hào)： | LTC1426IS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PWM D/A CONV 6BIT DUAL 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 6 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 550µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
6
LTC1426
APPLICATIONS INFORMATION
WU
U
where VPWM is the no load DAC output voltage, RL is the
resistive load and ROUT is the DAC output impedance.
Therefore, the resistive load RL should be sufficiently large
to ignore the effect of output impedance on the load
voltage.
Figure 2 shows a typical lowpass filter recommended to
filter the PWM outputs. Without filtering, results obtained
from unfiltered outputs can be erroneous when taking
measurements from a voltmeter. The ratio of the filter time
constant, t, to the PWM frequency determines the amount
of output ripple frequency that feeds into the system. In
addition, the loading of the output also determines an
additional error voltage drop across R1.
power-up, then the chip configures in pulse mode until
the next VCC reset.
Figure 3 shows the simplified logic for determining the
interface mode at power-up. A set of pull-up/pull-down
resistors allow the LTC1426 to sense the state of the CLK
pins at power-up. If both CLK1 and CLK2 pins are floating
on power-up then the control signal from the LTC1426
leaves these resistors in place, allowing the LTC1426 to
detect three operating states at each CLK pin: high, low
and “middle” (floating). If the CLK pins are tied to either
logic 0 or 1 at power-up, then the control signal will
disconnect these resistors, making CLK1 and CLK2 CMOS
compatible input pins.
Note that both CLK pins will always be in the same mode.
If one pin is floating and the other is at logic high/low on
power-up, the LTC1426 will assume pulse mode.
TYPICAL APPLICATIONS N
U
Typical applications for this part include digital calibration,
industrial process control, automatic test equipment, cel-
lular telephones and portable battery-powered applications.
Figures 4 and 5 show how easy this part is to use. In all
applications, the PWM full-scale output voltage is set by
VREF. This makes interfacing convenient when a variety of
reference spans are needed.
Pulse Mode
Figure 4 shows the LTC1426 in a pulse mode, stand-alone
application. The LTC1426 can interface directly with
minimum external components to most popular micro-
Figure 4. Stand-Alone Pulse Mode Interface
processors (MPUs). The Intel 8051 was chosen to dem-
onstrate direct interface for the LTC1426, as this
1
2
3
4
8
7
6
5
CLK1
CLK2
GND
PWM1
SHDN
VCC
VREF
PWM2
P1.0
P1.1
LTC1426
MPU
(e.g. 8051)
PWM1
1426 F04
PWM2
PWM1/PWM2: 0V TO 0.985(VREF)
0.1
F
VREF
0V TO 5.5V
VCC
2.7V TO 5.5V
SHDN
Figure 2. Lowpass Filter for PWM Averaging
C1
0.1
F
INPUT
OUTPUT
1426 F02
R1
10k
Digital Interface
The LTC1426 can be controlled by using one of two
interface modes: pulse mode and pushbutton mode. The
operating interface mode is determined during power-
up. If both CLK1 and CLK2 inputs are floating on power-up,
then an interface mode detect circuit configures the chip
in pushbutton mode until the next VCC reset (Figure 3).
However, if either of CLK1 or CLK2 is at logic 0 or 1 at
Figure 3. Interface Mode Detect Circuit
CLK1
CLK2
VCC
CLK1 INPUT
CLK2 INPUT
CONTROL
LTC1426
1426 F03
INTERNAL LOGIC
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