VCM SENSE VREF 1420 F02 – + R1 5k LOGIC" />
參數資料
型號: LTC1420CGN#TRPBF
廠商: Linear Technology
文件頁數: 20/20頁
文件大小: 0K
描述: IC ADC 12BIT 10MSPS SAMPL 28SSOP
標準包裝: 2,500
位數: 12
采樣率(每秒): 10M
數據接口: 并聯(lián)
轉換器數目: 1
功率耗散(最大): 300mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.154",3.90mm 寬)
供應商設備封裝: 28-SSOP
包裝: 帶卷 (TR)
輸入數目和類型: 2 個單端,雙極;1 個差分,雙極
9
LTC1420
1420fa
VCM
SENSE
VREF
1420 F02
+
R1
5k
LOGIC
2.5V
REFERENCE
2.048V
1F
1k
TO
ADC
R2
5k
VOUT
VIN
LT1019A-2.5
5V
1420 F03a
1F
VREF
SENSE
5V
VCM
LTC1420
1420 F03b
1F
VREF
LTC1420
SENSE
VCM
2.048V
+
5k
LTC1450
Figure 2. Reference Circuit
Figure 3a. Using the LT1019-2.5 As an
External Reference; Input Range = ±1.25V
Figure 3b. Driving VREF with a DAC
APPLICATIONS INFORMATION
WU
U
VREF and VREF can be driven by an external voltage. With
two additional resistors, VREF can be set to any voltage
between 2.048V and 4.5V.
An external reference or a DAC can be used to drive VREF
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the VREF pin is 1k, so a buffer may be
required for high accuracy. Driving VREF with a DAC is
useful in applications where the peak input signal ampli-
tude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.
Both the VCM and VREF pins must be bypassed with
capacitors to ground. For best performance, 1F or larger
ceramic capacitors are recommended. For the case of
external circuitry driving VREF, a smaller capacitor can be
used at VREF so the input range can be changed quickly. In
this case, a 0.05F or larger ceramic capacitor is accept-
able.
The VCM pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
applications it is convenient to connect – AIN directly to the
VCM pin.
Driving the Analog Inputs
The differential inputs of the LTC1420 are easy to drive.
The inputs may be driven differentially or single-ended
(i. e., the – AIN input is held at a fixed value). The – AIN and
+AIN inputs are simultaneously sampled and any com-
mon mode signal is reduced by the high common mode
rejection of the sample-and-hold circuit. Any common
mode input value is acceptable as long as the input pins
stay between VDD and VSS. During conversion, the analog
inputs are high impedance. At the end of conversion, the
inputs draw a small current spike while charging the
sample-and-hold.
For superior dynamic performance in dual supply mode,
the LTC1420 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. If required, the analog inputs
can be driven differentially via a transformer. Refer to
Table 2 for a summary of the analog input and reference
configurations and their relative advantages.
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