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參數(shù)資料
| 型號(hào)： | LTC1419ISW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit 200KSPS ADC Ser. Out, Auto PWRDN, Single Ended Input 8-MSOP -40 to 85 |
| 中文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-28 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 401K |
| 代理商： | LTC1419ISW |
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4
LTC1419
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with –A
IN
grounded.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 650ns after the start of the conversion or after BUSY rises.
(Note 5)
TW U
SYMBOL
P
DIS
PARAMETER
Power Dissipation
Nap Mode
Sleep Mode
CONDITIONS
MIN
TYP
150
7.5
1.2
MAX
240
12
UNITS
mW
mW
mW
G
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
POWER REQUIRW U
(Note 5)
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
ACQ + CONV
t
1
t
2
t
3
t
4
t
5
t
6
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition + Conversion Time
CS to RD Setup Time
CS
↓
to CONVST
↓
Setup Time
CS
↓
to SHDN
↓
Setup Time
SHDN
↑
to CONVST
↓
Wake-Up Time
CONVST
Low Time
CONVST to BUSY Delay
CONDITIONS
MIN
800
TYP
MAX
UNITS
kHz
G
G
950
90
1040
1150
300
1250
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
G
G
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
(Notes 10, 11)
C
L
= 25pF
G
0
G
40
40
400
G
40
20
G
50
t
7
Data Ready Before BUSY
↑
20
15
40
–5
50
G
t
8
t
9
t
10
Delay Between Conversions
Wait Time RD
↓
After BUSY
↑
Data Access Time After RD
↓
(Note 10)
G
G
C
L
= 25pF
15
25
35
35
50
20
25
30
G
C
L
= 100pF
20
G
t
11
Bus Relinquish Time
10
0
°
C
≤
T
A
≤
70
°
C
–40
°
C
≤
T
A
≤
85
°
C
G
G
t
12
t
13
RD Low Time
CONVST High Time
G
t
10
40
G
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3:
When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped
to V
DD
.
Note 5:
V
DD
= 5V, f
SAMPLE
= 800kHz, t
r
= t
f
= 5ns unless otherwise
specified.
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