參數(shù)資料
型號(hào)： LTC1419C
廠商： Linear Technology Corporation
英文描述： 14-Bit, 800ksps Sampling A/D Converter with Shutdown
中文描述： 14位，800ksps與關(guān)機(jī)采樣A / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 7/20頁(yè)
文件大小： 401K
代理商： LTC1419C
7
LTC1419
Load Circuits for Access Timing
Load Circuits for Output Float Delay
TEST CIR
1k
C
L
C
L
DBN
(A) Hi-Z TO V
OH
(B) Hi-Z TO V
OL
DBN
1k
5V
1419 TC01
1k
100pF
100pF
DBN
(A) V
OH
TO Hi-Z
(B) V
OL
TO Hi-Z
DBN
1k
5V
1419 TC02
APPLICATIO
S I
N
FOR
ATIO
U
CONVERSION DETAILS
The LTC1419 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs (please refer to Digital Interface section for
the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
W
U
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the +A
IN
and –A
IN
inputs are con-
nected to the sample-and-hold capacitors (C
SAMPLE
) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 200ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the C
SAMPLE
capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the +A
IN
and –A
IN
input charges.
The SAR contents (a 14-bit data word) which represents
the difference of +A
IN
and –A
IN
are loaded into the 14-bit
output latches.
DYNAMIC PERFORMANCE
The LTC1419 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algo-
rithm, the ADC’s spectral content can be examined for
Figure 1. Simplified Block Diagram
COMP
+C
SAMPLE
–C
DAC
D13
D0
ZEROING SWITCHES
HOLD
HOLD
+A
IN
–A
IN
+C
DAC
–C
SAMPLE
14
1419 F01
+
–
SAR
OUTPUT
LATCH
+V
DAC
–V
DAC
HOLD
HOLD
SAMPLE
SAMPLE
相關(guān)PDF資料
PDF描述
LTC1419CG 14-Bit, 800ksps Sampling A/D Converter with Shutdown
LTC1419CSW 14-Bit 200KSPS ADC Ser. Out, Auto PWRDN, Single Ended Input 8-SOIC -40 to 85
LTC1419I 14-Bit, 800ksps Sampling A/D Converter with Shutdown
LTC1419ISW 14-Bit 200KSPS ADC Ser. Out, Auto PWRDN, Single Ended Input 8-MSOP -40 to 85
LTC1419 14-Bit, 800ksps Sampling A/D Converter with Shutdown(12位, 800ksps,采樣模數(shù)轉(zhuǎn)換器(帶關(guān)斷))
相關(guān)代理商/技術(shù)參數(shù)
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LTC1419CGPBF 制造商:Linear Technology 功能描述:LTC1419CGPBF
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