參數(shù)資料
型號(hào)： LTC1418IN
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O
中文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PDIP28
封裝： 0.300 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 712K
代理商： LTC1418IN
4
LTC1418
TW U
(Note 5)
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
ACQ
+ t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition Plus Conversion Time
CS to RD Setup Time
CS
↓
to CONVST
↓
Setup Time
CS
↓
to SHDN
↓
Setup Time to Ensure Nap Mode
SHDN
↑
to CONVST
↓
Wake-Up Time from Nap Mode
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY
↑
CONDITIONS
MIN
200
TYP
MAX
UNITS
kHz
G
G
3.4
0.3
3.7
4
1
5
μ
s
μ
s
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
G
G
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
(Notes 10, 11)
CL = 25pF
G
0
G
40
40
G
500
G
40
G
35
35
70
20
15
500
–5
G
t
8
t
9
t
10
Delay Between Conversions
Wait Time RD
↓
After BUSY
↑
Data Access Time After RD
↓
(Note 10)
G
G
C
L
= 25pF
15
30
40
40
55
20
25
30
G
C
L
= 100pF
20
G
t
11
Bus Relinquish Time
8
Commercial
Industrial
G
G
t
12
t
13
t
14
t
15
f
SCLK
f
EXTCLKIN
t
dEXTCLKIN
t
H SCLK
t
L SCLK
t
H EXTCLKIN
t
L EXTCLKIN
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
CC
without latchup.
Note 4:
When these pin voltages are taken below V
SS
they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, V
SS
= 0V or –5V, f
SAMPLE
= 200kHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended input with A
IN–
grounded.
RD Low Time
CONVST High Time
Delay Time, SCLK
↓
to D
OUT
Valid
Time from Previous Data Remain Valid After SCLK
↓
Shift Clock Frequency
External Conversion Clock Frequency
Delay Time, CONVST
↓
to External Conversion Clock Input
SCLK High Time
SCLK Low Time
EXTCLKIN High Time
EXTCLKIN Low Time
G
t
10
40
C
L
= 25pF (Note 9)
C
L
= 25pF (Note 9)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
G
35
25
70
G
15
0
0.03
12.5
4.5
533
MHz
MHz
μ
s
ns
ns
ns
ns
10
20
250
250
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1
μ
s after the conversion starts or after BUSY rises.
Note 12:
Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.
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