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參數(shù)資料
| 型號(hào)： | LTC1417AIGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 27.5mW Unipolar; 44mW Bipolar |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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5
LTC1417
sn1417 1417fas
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tH SCLK
SCLK High Time
(Note 9)
q
10
ns
tL SCLK
SCLK Low Time
(Note 9)
q
10
ns
tH EXTCLKIN
EXTCLKIN High Time
q
0.04
20
s
tL EXTCLKIN
EXTCLKIN Low Time
q
0.04
20
s
fCLKOUT
Conversion Clock Output Frequency
Internal Conversion
9.4
MHz
Clock Mode (EXTCLKIN = 5V)
External Conversion Clock Mode
fEXTCLKIN
MHz
(EXTCLKIN is Driven by an External
Conversion Clock Input)
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA without latchup if the pin is driven below VSS (ground
for unipolar mode) or above VDD.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN+ input with AIN– grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 625ns after
conversion start or after BUSY rises.
Note 12: Typical RMS noise at the code transitions. See Figure 2 for
histogram.
Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising
capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with
5ns setup time.
TI I G CHARACTERISTICS
U
W
The q indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Typical INL Curve
Differential Nonlinearity
vs Output Code
S/(N + D) vs Input Frequency
and Amplitude
OUTPUT CODE
4096
0
–1.0
INL
(LSBs)
–0.5
0
0.5
1.0
8192
1417 G01
12288
16384
OUTPUT CODE
0
–1.0
DNL
ERROR
(LSBs)
– 0.5
0
0.5
1.0
4096
8192
1417 G02
12288
16384
(TA = 25°C, unless otherwise specified)
INPUT FREQUENCY (Hz)
SIGNAL/(NOISE
+
DISTORTION)
(dB)
90
80
70
60
50
40
30
20
10
0
1k
100k
1M
1417 G03
10k
VIN = –60dB
VIN = 0dB
VIN = –20dB
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