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參數(shù)資料
| 型號(hào)： | LTC1416IG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1346 (CN2011-ZH PDF) |
15
LTC1416
APPLICATIONS INFORMATION
WU
U
Figure 13. Power Supply Grounding Practice.
traces connecting the pins and bypass capacitors must be
kept short and should be made as wide as possible.
The LTC1416 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN– leads
will be rejected by the input CMRR. The AIN– input can be
used as a ground sense for the AIN+ input; the LTC1416
will hold and convert the difference voltage between AIN+
and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the AIN+ and AIN– traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, bypass
capacitors should be used at the VDD (10F) and REFCOMP
(22
F) pins as shown in the Typical Application on the first
page of this data sheet. Surface mount ceramic capacitors
such as Murata GRM235Y5V106Z016 provide excellent
bypassing in a small board space. Alternatively tantalum
capacitors in parallel with 0.1
F ceramic capacitors can be
used. Bypass capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Example Layout
Figures 14a, 14b, 14c and 14d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a 2-layer printed circuit board.
DIGITAL INTERFACE
The A/D converter is designed to interface with micropro-
cessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. A separate CONVST is used to initiate a con-
version.
Internal Clock
The A/D converter has an internal clock that eliminates the
need for synchronization between the external clock and
the CS and RD signals found in other ADCs. The internal
clock is factory trimmed to achieve a typical conversion
time of 1.8
s, and a maximum conversion time over the
full operating temperature range of 2.2
s. No external
adjustments are required. The guaranteed maximum
acquisition time is 400ns. In addition, a throughput time
of 2.5
s and a minimum sampling rate of 400ksps is
guaranteed.
Power Shutdown
The LTC1416 provides two power shutdown modes—nap
mode and sleep mode to save power during inactive
periods. The nap mode reduces the power by 95% and
leaves only the digital logic and reference powered up. The
wake-up time from nap to active is 400ns. In sleep mode,
the reference is shut down and only a small current of
120
A remains. Wake-up time from sleep mode is much
slower since the reference circuit must power up and
settle to 0.005% for full 14-bit accuracy. Sleep mode
wake-up time is dependent on the value of the capacitor
connected to the REFCOMP (Pin 4). The wake-up time is
20ms with the recommended 22
F capacitor.
1416 F13
10
F
10
F
ANALOG
INPUT
CIRCUITRY
5
4
2
26
28
27
14
1
22
F
DIGITAL
SYSTEM
AIN
+
AGND
REFCOMP
VSS
AVDD
LTC1416
DVDD
DGND
AIN
–
+
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