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參數(shù)資料
| 型號： | LTC1416CG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
4
LTC1416
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
400
kHz
tCONV
Conversion Time
q
1.5
1.9
2.2
s
tACQ
Acquisition Time
(Note 9)
q
100
400
ns
tACQ+CONV
Acquisition + Conversion Time
q
2
2.5
s
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓Setup Time
(Notes 9, 10)
q
10
ns
t3
CS
↓to SHDN↓Setup Time
(Notes 9, 10)
q
10
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time
CS = 0V (Note 10)
400
ns
t5
CONVST Low Time
(Notes 10, 11)
q
40
ns
t6
CONVST to BUSY Delay
CL = 25pF
25
ns
q
50
ns
t7
Data Ready Before BUSY
↑
(Note 9)
75
100
ns
q
50
ns
t8
Delay Between Conversions
(Note 10)
q
40
ns
t9
Wait Time RD
↓ After BUSY↑
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
25
ns
q
35
ns
CL = 100pF
20
35
ns
q
50
ns
t11
Bus Relinquish Time
820
ns
0
°C ≤ TA ≤ 70°C
q
25
ns
–40
°C ≤ TA ≤ 85°C
q
30
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
q
40
ns
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended AIN+ input with AIN– grounded.
POWER REQUIRE E TS
W
U
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ISS
Negative Supply Current
q
710
mA
Nap Mode
SHDN = 0V, CS = 0V
20
A
Sleep Mode
SHDN = 0V, CS = 5V
15
A
PDISS
Power Dissipation
q
70
100
mW
Power Dissipation, Nap Mode
SHDN = 0V, CS = 0V
4
6
mW
Power Dissipation, Sleep Mode
SHDN = 0V, CS = 5V
0.1
mW
The q denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
TI I G CHARACTERISTICS
U
W
The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5, see Figures 15 to 21)
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