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參數(shù)資料
| 型號： | LTC1416CG#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
12
LTC1416
APPLICATIONS INFORMATION
WU
U
reference amplifier compensation pin, REFCOMP (Pin 4),
must be bypassed with a capacitor to ground. The refer-
ence amplifier is stable with capacitors of 1
F or greater.
For the best noise performance, a 22
F ceramic or 22F
tantalum in parallel with a 0.1
F ceramic is recommended.
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1416 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
INPUT FREQUENCY (Hz)
1k
COMMON
MODE
REJECTION
(dB)
80
70
60
50
40
30
20
10
0
10k
100k
1416 G09
1M 2M
Figure 10a. CMRR vs Input Frequency
1
2
22
F
ANALOG INPUT
1416 F10b
AIN
+
AIN
–
LTC1416
REFCOMP
AGND
4
5
3
0V TO 5V
±2.5V
VREF
converts a 0V to 5V analog input signal with no additional
translation circuitry.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1416. The code transitions occur midway between
successive integer LSB values (i.e., – FS + 0.5LSB, – FS +
1.5LSB, – FS + 2.5LSB, . . . FS – 1.5LSB, FS – 0.5LSB). The
output is two’s complement binary with 1LSB = FS –
(– FS)/16384 = 5V/16384 = 305.2
V.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error, apply
– 152
V (i.e., –0.5LSB) at AIN+ and adjust the offset at the
AIN– input until the output code flickers between 0000
Figure 10b. Selectable 0V to 5V or
±2.5V Input Range
1
2
3
22
F
ANALOG
INPUT
1.25V TO 3V
1416 F09
AIN
+
AIN
–
VREF
LTC1416
LTC1450
REFCOMP
AGND
4
5
Figure 9. Driving VREF with a DAC
Differential Inputs
The LTC1416 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – AIN– independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies (see Figure 10a).
The only requirement is that both inputs cannot exceed the
AVDD or AVSS power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
mode voltage. THD will degrade as the inputs approach
either power supply rail, from 90dB with a common mode
of 0V to 79dB with a common mode of 2.5V or – 2.5V.
Differential inputs allow greater flexibility for accepting
different input ranges. Figure 10b shows a circuit that
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