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參數(shù)資料
| 型號(hào)： | LTC1416 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Low Power 14-Bit, 400ksps Sampling ADC |
| 中文描述： | 低功耗14位，以其400 kSPS采樣ADC |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 506K |
| 代理商： | LTC1416 |
4
LTC1416
SYMBOL
P
DISS
PARAMETER
Power Dissipation
Power Dissipation, Nap Mode
Power Dissipation, Sleep Mode
CONDITIONS
MIN
TYP
70
4
0.1
MAX
100
6
UNITS
mW
mW
mW
POWER REQUIREW
U
(Note 5)
G
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended A
IN+
input with A
IN–
grounded.
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 900ns after the
start of the conversion or after BUSY rises.
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
ACQ+CONV
t
1
t
2
t
3
t
4
t
5
t
6
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Acquisition + Conversion Time
CS to RD Setup Time
CS
↓
to CONVST
↓
Setup Time
CS
↓
to SHDN
↓
Setup Time
SHDN
↑
to CONVST
↓
Wake-Up Time
CONVST
Low Time
CONVST to BUSY Delay
CONDITIONS
MIN
400
1.5
TYP
MAX
UNITS
kHz
G
G
1.9
100
2
2.2
400
2.5
μ
s
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 9)
G
G
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
(Notes 10, 11)
C
L
= 25pF
G
0
10
10
G
G
400
G
40
25
G
50
t
7
Data Ready Before BUSY
↑
75
50
40
–5
100
G
t
8
t
9
t
10
Delay Between Conversions
Wait Time RD
↓
After BUSY
↑
Data Access Time After RD
↓
(Note 10)
G
G
C
L
= 25pF
15
25
35
35
50
20
25
30
G
C
L
= 100pF
20
G
t
11
Bus Relinquish Time
8
0
°
C
≤
T
A
≤
70
°
C
–40
°
C
≤
T
A
≤
85
°
C
G
G
t
12
t
13
RD Low Time
CONVST High Time
G
t
10
40
G
(Note 5, see Figures 15 to 21)
TW U
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals at T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3:
When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, V
SS
= –5V, f
SAMPLE
= 400kHz, t
r
= t
f
= 5ns unless
otherwise specified.
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