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參數(shù)資料
| 型號： | LTC1415ISW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT SAMPLNG 28SOIC |
| 標準包裝： | 27 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
4
LTC1415
(Note 5)
TI I G CHARACTERISTICS
W U
The q denotes specifications which apply over the full operating
temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below ground or above VDD,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above VDD without latchup.
Note 4: When these pin voltages are taken below ground, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below ground without latchup. These pins are not clamped
to VDD.
Note 5: VDD = 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise
specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +AIN input with – AIN grounded.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion it can create small
errors. For best performance ensure that CONVST returns high either
within 425ns after the start of the conversion or after BUSY rises.
Note 12: CS = RD = CONVST = 0V.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
1.25
MHz
Conversion and Acquisition Time
q
800
ns
tCONV
Conversion Time
q
700
ns
tACQ
Acquisition Time
q
150
ns
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓Setup Time
(Notes 9, 10)
q
10
ns
t3
NAP/SLP
↑to SHDN↓Setup Time
(Notes 9, 10)
200
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10)
200
ns
Sleep Mode, CREFCOMP = 10F (Note 10)
10
ms
t5
CONVST Low Time
(Notes 10, 11)
q
50
ns
t6
CONVST to BUSY Delay
CL = 25pF
10
ns
q
60
ns
t7
Data Ready Before BUSY
↑
20
35
ns
q
15
ns
t8
Delay Between Conversions
(Note 10)
q
50
ns
t9
Wait Time RD
↓ After BUSY↑
(Note 10)
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
20
35
ns
q
45
ns
CL = 100pF
25
45
ns
q
60
ns
t11
Bus Relinquish Time
10
30
ns
0
°C = TA = 70°C
q
35
ns
–40
°C = TA = 85°C
q
40
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
q
50
ns
t14
Aperture Delay of Sample-and-Hold
– 1.5
ns
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