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參數(shù)資料
| 型號： | LTC1414CGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/20頁 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
13
LTC1414
APPLICATIONS INFORMATION
WU
U
Figure 14. Offset and Full-Scale Adjust Circuit
LTC1414
AIN
+
ANALOG INPUT
AIN
–
VREF
REFCOMP
AGND
LTC1414 F14
1
2
3
R4
100
R2
50k
R3
24k
–5V
R6
24k
R1
50k
R5
47k
4
5
10
F
Board Layout and Bypassing
To obtain the best performance from the LTC1414, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital line alongside an analog signal line or underneath
the ADC. The analog input should be screened by AGND.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD, VSS and VREF pins. Bypass
capacitors must be located as close to the pins as possible.
The traces connecting the pins and bypass capacitors
must be kept short and should be made as wide as
possible.
The LTC1414 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN–
inputs will be reflected by the input CMRR. The AIN– input
can be used as a ground sense for the AIN+ input; the
LTC1414 will hold and convert the difference voltage
between AIN+ and AIN–. The leads to AIN+ (Pin 1) and AIN–
(Pin 2) should be kept as short as possible. In applications
where this is not possible, the AIN+ and AIN– traces should
be run side by side to equalize coupling.
A single point analog ground separate from the logic
system ground should be established with an analog
ground plane at AGND (Pin 5, 27) or as close as possible
to the ADC (see Figure 8). The ADC’s DGND (Pin 23) and
all other analog grounds should be connected to this
single analog ground point. No other digital grounds
should be connected to this analog ground point. Low
impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
these traces should be as wide as possible. Excessive
capacitive loading on the ADC’s data output lines can
generate large transient currents on the ADC supplies
which may affect conversion results. In these cases, the
use of digital buffers is recommended to isolate the ADC
from the excessive loading.
EXAMPLE LAYOUT
Figures 16a, 16b, 16c and 16d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
1414 F15
AIN
+
AGND
REFCOMP
VSS
AVDD
LTC1414
DIGITAL
SYSTEM
ANALOG
INPUT
CIRCUITRY
5, 27
4
2
26
28
OVDD
21
OGND
DGND
14
23
1
10
F
AIN
–
10
F
10
F
DVDD
22
ANALOG GROUND PLANE
+
–
Figure 15. Power Supply Grounding Practice
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