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參數(shù)資料
| 型號： | LTC1414CGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 2.2MSPS SMPL 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 230mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
12
LTC1414
APPLICATIONS INFORMATION
WU
U
The VREF pin can be driven with a DAC or other means
shown in Figure 11. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1414 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed after a reference adjustment.
The output is two’s complement binary with
1LSB = FS – (– FS)/16384 = 5V/16384 = 305.2
V.
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 14
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error apply
– 152
V (i.e., –0.5LSB) at AIN+ and adjust the offset at the
AIN– input until the output code flickers between 0000
0000 0000 00 and 1111 1111 1111 11. For full-scale
adjustment, an input voltage of 2.499544V (FS – 1.5LSBs)
is applied to AIN+ and R2 is adjusted until the output
code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
Figure 11. Driving VREF with a DAC
LTC1414
AIN
+
ANALOG INPUT
±2V TO ±3V
DIFFERENTIAL
AIN
–
VREF
REFCOMP
AGND
1414 F11
1
2
3
4
5
10
F
LTC1450
2V TO 3V
Differential Inputs
The LTC1414 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – (AIN–) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 12. The
only requirement is that neither input can exceed the AVDD
or AVSS power supply voltages. Integral nonlinearity er-
rors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
mode voltage. THD will degrade as the inputs approach
either power supply rail, from –84dB with a common
mode of 0V to –75dB with a common mode of 2.5V
or –2.5V.
Full-Scale and Offset Adjustment
Figure 13 shows the ideal input/output characteristics for
the LTC1414. The code transitions occur midway between
successive integer LSB values (i.e., – FS + 0.5LSB,
– FS + 1.5LSB, – FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB).
Figure 12. CMRR vs Input Frequency
INPUT FREQUENCY (Hz)
1k
COMMON
MODE
REJECTION
(dB)
80
70
60
50
40
30
20
10
0
10k
100k
LTC1414 F12
1M
10M
Figure 13. LTC1414 Transfer Characteristics
INPUT RANGE
OUTPUT
CODE
LTC1414 F13
011…111
011…110
011…101
000…000
111…111
100…000
100…001
100…010
FS – 1LSB
0
–(FS – 1LSB)
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