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參數(shù)資料
| 型號(hào)： | LTC1412CG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT SAMPLNG 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 220mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
12
LTC1412
APPLICATIONS INFORMATION
WU
U
LTC1412
AIN
+
ANALOG INPUT
5V
AIN
–
VREF
REFCOMP
AGND
1412 F08b
1
2
3
4
5
10
F
VIN
VOUT
LT1019A-2.5
RIPPLE FREQUENCY (Hz)
–80
AMPLITUDE
OF
POWER
SUPPLY
FEEDTHROUGH
(dB)
–40
0
–100
–60
–20
10k
100k
1M
10M
1412 G08
–120
1k
VSS
VDD
DGND
mode voltage. THD will degrade as the inputs approach
either power supply rail, from – 86dB with a common
mode of 0V to –75dB with a common mode of 2.5V
or – 2.5V.
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics for
the LTC1412. The code transitions occur midway between
successive integer LSB values (i.e., – FS/2 + 0.5LSB,
– FS/2 + 1.5LSB, – FS/2 + 2.5LSB,...FS/2 – 1.5LSB, FS/2 –
0.5LSB). The output is two’s complement binary with
1LSB = FS – (– FS)/4096 = 5V/4096 = 1.22mV.
Differential Inputs
The LTC1412 has a unique differential sample-and-hold
circuit that allows rail-to-rail inputs. The ADC will always
convert the difference of AIN+ – (AIN–) independent of the
common mode voltage. The common mode rejection
holds up to extremely high frequencies, see Figure 10. The
only requirement is that both inputs cannot exceed the
AVDD or AVSS power supply voltages. Integral nonlinearity
errors (INL) and differential nonlinearity errors (DNL) are
independent of the common mode voltage, however, the
bipolar zero error (BZE) will vary. The change in BZE is
typically less than 0.1% of the common mode voltage.
Dynamic performance is also affected by the common
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the AIN– input. For zero offset error apply
Figure 10. CMRR vs Input Frequency
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means
shown in Figure 9. This is useful in applications where the
peak input signal amplitude may vary. The input span of
the ADC can then be adjusted to match the peak input
signal, maximizing the signal-to-noise ratio. The filtering
of the internal LTC1412 reference amplifier will limit the
bandwidth and settling time of this circuit. A settling time
of 5ms should be allowed for after a reference adjustment.
LTC1412
AIN
+
ANALOG INPUT
1.25V TO 3V
DIFFERENTIAL
AIN
–
VREF
REFCOMP
AGND
1412 F09
1
2
3
4
5
10
F
LTC1450
1.25V TO 3V
Figure 9. Driving VREF with a DAC
INPUT VOLTAGE (V)
OUTPUT
CODE
1412 F11a
111...111
111...110
111...101
000...000
000...001
000...010
FS – 1LSB
Figure 11a. LTC1412 Transfer Characteristics
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