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參數(shù)資料
| 型號(hào)： | LTC1409DWF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC28 |
| 封裝： | 90 X 155 MM, WAFER-28 |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大小： | 59K |
| 代理商： | LTC1409DWF |
DICE/DWF SPECIFICATION
2
LTC1409
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006
LT 0506 PRINTED IN USA
Wafer level testing is performed per the indicated specications for dice. Considerable differences in performance can often be observed for dice versus
packaged units due to the inuences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information
on dice performance and lot qualications via lot sampling test procedures. Standard binning is by ink dot of reject die.
Dice data sheet subject to change. Please consult factory for current revision in production.
I.D.No. 66-13-1409
DICE/DWF ELECTRICAL TEST LIMITS TA = 25°C unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latch-up.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, fSAMPLE = 800kHz, tr = tf = 5ns unless otherwise
specied.
Note 6: Linearity, offset and full-scale specications apply for a single-
ended +AIN input with –AIN grounded.
Note 7: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB when
the output code ickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 650ns after
conversion start or after BUSY rises.
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
Analog Input (Note 5)
VIN
Analog Input Range
4.75V ≤ VDD ≤ 5.25V, –5.25V ≤ VSS ≤ –4.75V
V
IIN
Analog Input Leakage Current
CS = High
±1
A
Internal Reference Characteristics (Note 5)
VREF Output Voltage
IOUT = 0
2.480
2.520
V
Digital Inputs and Digital Outputs (Note 5)
VIH
High Level Input Voltage
VDD = 5.25V
2.4
V
VIL
Low Level Input Voltage
VDD = 4.75V
0.8
V
IIN
Digital Input Current
VIN = 0V to VDD
±10
A
VOH
High Level Output Voltage
VDD = 4.75V, IO = –200A
4
V
VOL
Low Level Output Voltage
VDD = 4.75V, IO = 1.6mA
0.4
V
IOZ
Hi-Z Output Leakage D11 to D0
VOUT = 0V to VDD, CS High
±10
A
Power Requirements (Note 5)
VDD
Positive Supply Voltage
(Note 9)
4.75
5.25
V
VSS
Negative Supply Voltage
–4.75
–5.25
V
IDD
Positive Supply Current
Nap Mode
CS High
CONVST = CS = RD = SHDN = 0V, NAP/SLP = 5V
9.0
1.2
mA
ISS
Negative Supply Current
CS High
15
mA
Timing Characteristics (Note 5)
fSAMPLE(MAX)
Maximum Samping Frequency
800
kHz
tCONV
Conversion Time
1250
ns
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