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參數(shù)資料
| 型號(hào)： | LTC1401CS8#TR |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 200KSPS SHTDN 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)單端，單極 |
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12
LTC1401
1401fa
APPLICATIONS INFORMATION
WU
U
circuitry. In this mode, the ADC draws only 1.5mW of
power instead of 15mW (for minimum power, the logic
inputs must be within 500mV of the supply rails). The
wake-up time from Nap mode to active mode is 350ns. In
Sleep mode, power consumption is reduced to 19.5
W by
cutting off the supply to the comparator and reference.
Figure 11 illustrates power-down methods for the LTC1401.
The chip enters Nap mode by keeping the CLK signal low
and pulsing the CONV signal twice. For Sleep mode
operation, CONV signal should be pulsed four times while
CLK is kept low. NAP and SLEEP modes are activated on
the falling edge of the CONV pulse. By pulling SHDN low,
the LTC1401 enters Shutdown mode and power con-
sumption drops to 13.5
W.
Once SHDN goes high, the LTC1401 returns to active
mode or the LTC1401 returns to active mode by pulsing
the CLK signal if the device has entered Nap/Sleep mode.
During the transistion from Sleep mode to active mode,
the VREF voltage ramp-up time is a function of its loading
conditions. With a 10
F bypass capacitor, the wake-up
time from Sleep mode is typically 3ms. A REFRDY signal
is activated once the reference has settled and is ready for
an A/D conversion. This REFRDY bit is sent to the DOUT pin
as the first bit followed by the 12-bit data word (refer to
Figure 12).
DIGITAL INTERFACE
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the DOUT output provides
the conversion result in serial form.
Figures 12 and 13 show the digital timing waveform of the
LTC1401 during the Analog to Digital Conversion. The
CONV rising edge starts the conversion. Once initiated, it
can not be restarted until the conversion is completed. If
the time from the CONV signal to the CLK rising edge is
less than t2, the digital output will be delayed by one clock
cycle.
The digital output data is updated on the rising edge of the
CLK line. The digital output data consists of a REFRDY bit
followed by the valid 12-bit data word. DOUT data should
be captured by the receiving system on the rising CLK
edge. Data remains valid for a minimum time of t10 after
the rising CLK edge to allow capture to occur.
Figure 11. Nap Mode and Sleep Mode Waveforms
CLK
CONV
NAP
SLEEP
VREF
t1
t11
t1
REFRDY
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS THE FIRST BIT IN THE DOUT WORD.
LTC1401 F11
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