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參數(shù)資料
| 型號(hào)： | LTC1400CS8 |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 12BIT W/SHTDN 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 160mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極；1 個(gè)單端，雙極 |
LTC1400
13
1400fa
APPLICATIO S I FOR ATIO
W
U
In the Sleep mode, power consumption is reduced to a
minimum by cutting off the supply to all internal circuitry
includingthereference.Figure12showsthewaystopower
down the LTC1400. The chip can enter the Nap mode by
keeping the CLK signal low and pulsing the CONV signal
twice. For Sleep mode operation, CONV signal should be
pulsed four times while CLK is kept low.
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
transition from Sleep mode to active mode, the VREF volt-
age ramp-up time is a function of the loading conditions.
With a 10μF bypass capacitor, the wake-up time from
Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for
an A/D conversion. This REFRDY bit is output to the DOUT
pin before the rest of the A/D converted code.
Digital Interface
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the DOUT output provides
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t2, the digital output will
be delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. DOUT data should be captured by the receiving
system on the rising CLK edge. Data remains valid for a
minimum time of t10 after the rising CLK edge to allow
capture to occur.
CLK
CONV
INTERNAL
S/H STATUS
DOUT
t7
t3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
t2
t6
t4
t5
t8
tACQ
SAMPLE
HOLD
Hi-Z
tCONV
tSAMPLE
1400 F13
REFRDY D11
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
REFRDY
Figure 13. ADC Digital Timing Diagram
Figure 14. CLK to DOUT Delay
t10
t8
VIH
VOH
VOL
DOUT
CLK
t9
VIH
90%
10%
DOUT
CLK
1400 F14
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| LTC1400CS8#PBF | 功能描述:IC A/D CONV 12BIT W/SHTDN 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| LTC1400CS8#TR | 功能描述:IC ADC 12BIT 400KSPS SHTDN 8SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC1400CS8#TRPBF | 功能描述:IC A/D CONV 12BIT W/SHTDN 8-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
| LTC1400CS8PBF | 制造商:Linear Technology 功能描述:LTC1400CS8PBF |
| LTC1400IS8 | 功能描述:IC A/D CONV 12BIT W/SHTDN 8-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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