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參數(shù)資料
| 型號(hào)： | LTC1400CS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Hex 2-Input OR Drivers 20-PDIP 0 to 70 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 515K |
| 代理商： | LTC1400CS8 |
4
LTC1400
(Note 5)
DIGITAL U
D OUTPUTS
U
SYMBOL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
(Note 7)
Output Source Current
Output Sink Current
CONDITIONS
V
OUT
= 0V to V
CC
MIN
TYP
MAX
±
10
UNITS
G
μ
A
pF
mA
mA
15
–10
10
V
OUT
= 0
V
OUT
= V
CC
TW U
(Note 5)
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time (Unipolar Mode)
CONDITIONS
(Note 6)
f
CLK
= 6.4MHz
(Note 7)
MIN
400
TYP
MAX
UNITS
kHz
G
G
2.1
300
270
6.4
μ
s
ns
ns
G
G
230
200
(Bipolar Mode V
SS
= –5V)
f
CLK
t
CLK
t
WK(NAP)
t
1
t
2
t
3
t
4
t
5
t
6
t
7
CLK Frequency
CLK Pulse Width
Time to Wake Up from Nap Mode
CLK Pulse Width to Return to Active Mode
CONV
↑
to CLK
↑
Setup Time
CONV
↑
After Leading CLK
↑
CONV Pulse Width
Time from CLK
↑
to Sample Mode
Aperture Delay of Sample-and-Hold
Minimum Delay Between Conversion (Unipolar Mode)
G
0.1
50
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 7)
(Note 7)
G
350
G
50
80
0
50
G
G
(Note 11)
(Note 7)
Jitter < 50ps (Note 7)
G
80
45
265
235
40
40
25
G
65
385
355
80
80
G
G
(Bipolar Mode V
SS
= –5V)
t
8
t
9
t
10
Delay Time, CLK
↑
to D
OUT
Valid
Delay Time, CLK
↑
to D
OUT
Hi-Z
Time from Previous Data Remains Valid After CLK
↑
C
LOAD
= 20pF
C
LOAD
= 20pF
C
LOAD
= 20pF
G
G
G
14
The
G
denotes specifications which apply over the full operating
temperature range; all other limits and typicals T
A
= 25
°
C.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
When these pin voltages are taken below V
SS
(ground for unipolar
mode) or above V
CC
, they will be clamped by internal diodes. This product
can handle input currents greater than 40mA below V
SS
(ground for
unipolar mode) or above V
CC
without latch-up.
Note 4:
When these pin voltages are taken below V
SS
(ground for unipolar
mode), they will be clamped by internal diodes. This product can handle
input currents greater than 40mA below V
SS
(ground for unipolar mode)
without latch-up. These pins are not clamped to V
CC
.
Note 5:
V
CC
= 5V, f
SAMPLE
= 400kHz, t
r
= t
f
= 5ns unless otherwise
specified.
Note 6:
Recommended operating conditions.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
Linearity, offset and full-scale specifications apply for unipolar and
bipolar modes.
Note 9:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 10:
Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 11:
The rising edge of CONV starts a conversion. If CONV returns
low at a bit decision point during the conversion, it can create small errors.
For best performance ensure that CONV returns low either within 120ns
after conversion starts (i.e., before the first bit decision) or after the 14
clock cycle. (Figure 13 Timing Diagram).
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