3
LTC1380/LTC1393
ELECTRICAL CHARACTERISTICS (Notes 2, 4)
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All current into device pins is positive; all current out of device
pins is negative. All voltages are referenced to ground unless otherwise
specified. All typicals are given for TA = 25°C, VCC = 5V (for both LTC1380
and LTC1393) and VEE = – 5V (LTC1380).
Note 3: These typical parameters are based on bench measurements and
are not production tested.
Note 4: Both SCL and SDA assume an external 15k pull-up resistor to a
typical SMBus host power supply VDD of 5V.
Note 5: Typical curves with VEE = – 5V apply to the LTC1380. Curves with
VEE = 0V apply to both the LTC1380 and the LTC1393.
Note 6: These parameters are guaranteed by design and are not tested in
production.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
SCL, SDA Input High Voltage
q
1.4
V
VIL
SCL, SDA Input Low Voltage
q
0.6
V
VOL
SDA Output Low Voltage
ISDA = 3mA
q
0.4
V
VAH
Address Input High Voltage
VCC = 5V
q
2V
VAL
Address Input Low Voltage
VCC = 5V
q
0.8
V
IIN
SCL, SDA, Address Input Current
0V
≤ VIN ≤ VCC
±1
A
ICC
Positive Supply Current
VCC = 5V, All Digital Inputs at 5V
q
10
20
A
IEE
Negative Supply Current
LTC1380: VCC = 5V, VEE = – 5V, All Digital Inputs at 5V
q
– 0.1
– 5
A
CS
Input Off Capacitance
(Note 3)
3
pF
CD
Output Off Capacitance
(Note 3) LTC1380
26
pF
LTC1393
18
pF
tON
Switch Turn-On Time from
Figure 1 LTC1380: VCC = 5V, VEE = – 5V
q
850
1500
ns
Stop Condition
LTC1393: VCC = 5V
q
850
1500
ns
LTC1380/LTC1393: VCC = 2.7V, VEE = 0V
q
1130
2000
ns
tOFF
Switch Turn-Off Time from
Figure 1 LTC1380: VCC = 5V, VEE = – 5V
q
640
1200
ns
Stop Condition
LTC1393: VCC = 5V
q
650
1200
ns
LTC1380/LTC1393: VCC = 2.7V, VEE = 0V
q
670
1200
ns
tOPEN
Break-Before-Make Interval
tON – tOFF
q
75
210
ns
OIRR
Off-Channel Isolation
Figure 2, VS = 200mVP-P, RL = 1k, f = 100kHz (Note 3)
– 65
dB
QINJ
Charge Injection
Figure 3, CL = 1000pF (Note 3)
q
±1
±20
pC
SMBus Timing (Note 6)
fSMB
SMBus Operating Frequency
q
100
kHz
tBUF
Bus Free Time Between Stop/Start
q
4.7
s
tHD:STA
Hold Time After (Repeated) Start
q
4.0
s
tSU:STA
Repeated Start Setup Time
q
4.7
s
tSU:STO
Stop Condition Setup Time
q
4.0
s
tHD:DAT
Data Hold Time
q
300
ns
tSU:DAT
Data Setup Time
q
250
ns
tLOW
Clock Low Period
q
4.7
s
tHIGH
Clock High Period
q
4.0
s
tf
SCL/SDA Fall Time
Time Interval Between 0.9VDD and (VILMAX – 0.15)
q
300
ns
tr
SCL/SDA Rise Time
Time Interval Between (VILMAX – 0.15)
q
1000
ns
and (VIHMIN + 0.15)