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參數(shù)資料
| 型號： | LTC1380IS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Single-Ended 8-Channel/ Differential 4-Channel Analog Multiplexer with SMBus Interface |
| 中文描述： | 8-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SO-16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 275K |
| 代理商： | LTC1380IS |
6
LTC1380/LTC1393
PI
FU
CTIO
N
S
U
U
S0 to S7/S0
±
to S3
±
(Pin 1 to Pin 8):
Single-Ended Analog
Multiplexer Inputs (S0 to S7) for the LTC1380. Differential
Analog Multiplexer Inputs (S0
±
to S3
±
) for the LTC1393.
D
O
/D
O+
(Pin 9):
Analog Multiplexer Output for the LTC1380.
Positive Differential Analog Multiplexer Output for the
LTC1393.
V
EE
/D
O–
(Pin 10):
Negative Supply Pin for the LTC1380.
Negative Differential Multiplexer Output for the LTC1393.
For the LTC1380, V
EE
should be bypassed to GND with a
0.1
μ
F ceramic capacitor when operating from split sup-
plies or connected to GND for single supply operation.
GND (Pin 11):
Ground Pin.
A1, AO (Pin 12, Pin 13):
Address Selection Pins. Tie these
two pins to either V
CC
or GND to select one of four possible
addresses to which the LTC1380/LTC1393 will respond.
SDA (Pin 14):
SMBus Bidirectional Digital Input/Output
Pin. This pin has an open-drain output and requires a pull-
up resistor or current source to the positive supply for
normal operation. Data is shifted into and acknowledged
by the LTC1380/LTC1393 using this pin.
SCL (Pin 15):
SMBus Clock Input. SDA data is shifted in
at rising edges of this clock during data transfer.
V
CC
(Pin 16):
Positive Supply Pin. This pin should be
bypassed to GND with a 0.1
μ
F ceramic capacitor.
BLOCK DIAGRA
ADDRESS
COMPARATOR
SMBus STATE
MACHINE
4-BIT LATCH
AND DECODER
SHIFT REGISTER
HOLD
STOP
1380/93 BD
SDA
A0
A1
SCL
MULTIPLEXER
SWITCHES
ANALOG OUTPUT(S)
(LTC1380: D
O
)
(LTC1393: D
O
±
)
ANALOG INPUTS
(LTC1380: S0 TO S7)
(LTC1393: S0
±
TO S3
±
)
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PDF描述 |
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