
3
LTC1329-10/
LTC1329-50/LTC1329A-50
VCC = 3.3V, unless otherwise specified. (Notes 2, 3)
RECO
E DED OPERATI G CO DITIO S
U
UW
W
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Interface
fCLK
Clock Frequency
q
2
MHz
tCKS
Setup Time, CLK
↓ Before CS↓
q
150
ns
tCSS
Setup Time, CS
↓ Before CLK↑
q
400
ns
tDV
CS
↓ to DOUT Valid
See Test Circuits
q
150
ns
tDS
DIN Setup Time Before CLK↑
q
150
ns
tDH
DIN Hold Time After CLK↑
q
150
ns
tDO
CLK
↓ to DOUT Valid
See Test Circuits
q
150
ns
tCKHI
CLK High Time
q
200
ns
tCKLO
CLK Low Time
q
250
ns
tCSH
CLK
↓ Before CS↑
q
150
ns
tDZ
CS
↑ to DOUT in Hi-Z
See Test Circuits
q
400
ns
tCKH
CS
↑ Before CLK↑
q
400
ns
tCSLO
CS Low Time
fCLK = 2MHz (Note 4)
q
4550
ns
VCLK = 0V
q
400
ns
tCSHI
CS High Time
q
400
ns
Note 2: Timing for all input signals is measured at 0.8V for a High-to-Low
transition and at 2V for a Low-to-High transition.
Note 3: Timing specification are guaranteed but not tested.
Note 4: This is the minimum time required for valid data transfer.
The q denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
TYPICAL PERFORMANCE CHARACTERISTICS
U
W
CODE
0
DNL
(LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
64
128
160
1392 G01
32
96
192 224
256
TA = 25°C
VCC = 3.3V
V(IOUT) = 0.45V
CODE
0
INL
(LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
64
128
160
1329 TPC02
32
96
192 224
256
TA = 25°C
VCC = 3.3V
V(IOUT) = 0.45V
CODE
0
DNL
(LSB)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
64
128
160
1392 G03
32
96
192 224
256
TA = 25°C
VCC = 3.3V
V(IOUT) = 0.45V
LTC1329-10 DNL vs Code
LTC1329-10 INL vs Code
LTC1329-50 DNL vs Code