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參數(shù)資料
| 型號： | LTC1297DIN8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Single Chip 12-Bit Data Acquisition Systems |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 466K |
| 代理商： | LTC1297DIN8 |
16
LTC1292/LTC1297
Figure 12. “+” and “–” Input Settling Windows for the LTC1297
“–” input voltage be free of noise and settle completely
during the first CLK cycle of the conversion. Minimizing
R
SOURCE
– and C2 will improve settling time. If large “–”
input source resistance must be used the time can be
extended by using a slower CLK frequency. At the maximum
CLK frequency of 1MHz,
R
SOURCE
– < 250
and C2 < 20pF
will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
(see Figures 11a, 11b, 11c and 12). Again the “+” and
“–” input sampling times can be extended as described
above to accommodate slower op amps. Most op amps
including the LT1006 and LT1013 single supply op amps
can be made to settle well even with the minimum settling
windows of 3.0
μ
s for the LTC1292 or 6.0
μ
s for the
LTC1297 (“+” input) and 1
μ
s (“–” input) that occurs at the
maximum clock rate of 1MHz. Figures 13 and 14 show
examples of both adequate and poor op amp settling.
V
HORIZONTAL: 500ns/DIV
HORIZONTAL: 20
μ
s/DIV
Figure 13. Adequate Settling of Op Amp Driving Analog Input
V
Figure 14. Poor Op Amp Settling Can Cause A/D Errors
U
S
A
O
PPLICATI
U
U
D
OUT
CLK
B11
HI-Z
B10
LTC1292/7 F12
CS
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
t
WHCS
t
SMPL
(+) INPUT MUST SETTLE
DURING THIS TIME
(+) INPUT
(–) INPUT
t
suCS
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