Usually VERROR will not be significant. For a 60Hz " />
參數(shù)資料
型號(hào)： LTC1296DISW
廠商： Linear Technology
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ SYSTEM 12BIT 20-SOIC
標(biāo)準(zhǔn)包裝： 38
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 12 b
采樣率（每秒）： 46.5k
數(shù)據(jù)接口： 串行，并聯(lián)
電壓電源： 雙 ±
電源電壓： ±5V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC
包裝： 管件
21
LTC1293/LTC1294/LTC1296
129346fs
Usually VERROR will not be significant. For a 60Hz signal
on the “–” input to generate a 0.25LSB error (300
V) with
the converter running at CLK = 1MHz, its peak value would
have to be 66mV. Rearranging the above equation the
maximum sinusoidal signal that can be digitized to a given
accuracy is given as:
For 0.25LSB error (300
V) the maximum input sinusoid
with a 5V peak amplitude that can be digitized is 0.8Hz.
Unused inputs should be tied to the ground plane.
Reference Input
The voltage on the reference input of the LTC1293/4/6
determines the voltage span of the A/D converter. The
reference input has transient capacitive switching cur-
rents due to the switched capacitor conversion technique
(see Figure 12). During each bit test of the conversion
(every CLK cycle) a capacitive current spike will be gener-
ated on the reference pin by the A/D. These current spikes
settle quickly and do not cause a problem. If slow settling
circuitry is used to drive the reference input, take care to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time for
the reference to settle. Even at the maximum CLK rate of
1MHz most references and op amps can be made to settle
within the 1
s bit time. For example the LT1027 will settle
adequately or with a 10
F bypass capacitor at VREF the
LT1021 also can be used.
VERTICAL:
0.5mV/DIV
VERTICAL:
0.5mV/DIV
Figure 14. Poor Reference Settling Can Cause A/D Errors
HORIZONTAL: 1
s/DIV
HORIZONTAL: 1
s/DIV
Figure 13. Adequate Reference Settling (LT1027)
Figure 12. Reference Input Equivalent Circuit
RON
8pF – 40pF
LTC1293/4/6
REF+
ROUT
VREF
EVERY CLK CYCLE
14
13
REF–
LTC 1293 F12
Reduced Reference Operation
The effective resolution of the LTC1293/4/6 can be in-
creased by reducing the input span of the converter. The
LTC1293/4/6 exhibits good linearity over a range of refer-
ence voltages (see typical performance characteristics
curves of Change in Linearity vs Reference Voltage and
Change in Gain Error vs Reference Voltage). Care must be
taken when operating at low values of VREF because of the
reduced LSB step size and the resulting higher accuracy
requirement placed on the converter. Offset and Noise are
factors that must be considered when operating at low
VREF values. For the LTC1293 REF– has been tied to the
AGND pin. Any voltage drop from the AGND pin to the
ground plane will cause a gain error.
Offset with Reduced VREF
The offset of the LTC1293/4/6 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size of
the LSB is reduced. The typical performance characteris-
tic curve of Unadjusted Offset Error vs Reference Voltage
shows how offset in LSB’s is related to reference voltage
for a typical value of VOS. For example a VOS of 0.1mV,
which is 0.1LSB with a 5V reference becomes 0.4LSB with
f
V
f
MAX
ERROR MAX
PEAK
CLK
(–)
()
=
π
2
12
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LTC1296DISW#TRPBF 功能描述:IC DATA ACQ SYSTEM 12BIT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤(pán)
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