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  • 參數(shù)資料
    型號: LTC1294CCN
    廠商: Linear Technology
    文件頁數(shù): 11/28頁
    文件大?。?/td> 0K
    描述: IC DATA ACQ SYSTEM 12BIT 20-DIP
    標(biāo)準(zhǔn)包裝: 18
    類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
    分辨率(位): 12 b
    采樣率(每秒): 46.5k
    數(shù)據(jù)接口: 串行,并聯(lián)
    電壓電源: 雙 ±
    電源電壓: ±5V,5V
    工作溫度: 0°C ~ 70°C
    安裝類型: 通孔
    封裝/外殼: 20-DIP(0.300",7.62mm)
    供應(yīng)商設(shè)備封裝: 20-PDIP
    包裝: 管件
    19
    LTC1293/LTC1294/LTC1296
    129346fs
    U
    S
    A
    O
    PPLICATI
    WU
    U
    I FOR ATIO
    Source Resistance
    The analog inputs of the LTC1293/4/6 look like a 100pF
    capacitor (CIN) in series with a 500 resistor (RON). CIN
    gets switched between (+) and (–) inputs once during each
    conversion cycle. Large external source resistors and
    capacitances will slow the settling of the inputs. It is
    important that the overall RC time constant is short
    enough to allow the analog inputs to settle completely
    within the allowed time.
    “+” Input Settling
    The input capacitor is switched onto the “+” input during
    the sample phase (tSMPL, see Figure 8). The sample period
    2 1/2 CLK cycles before a conversion starts. The voltage on
    the “+” input must settle completely within the sample
    period. Minimizing RSOURCE+ and C1 will improve the
    settling time. If large “+” input source resistance must be
    used, the sample time can be increased by using a slower
    CLK frequency. With the minimum possible sample time
    of 2.5
    s RSOURCE+ < 1.5k
    and C1 < 20pF will provide
    adequate settling time.
    “–” Input Settling
    At the end of the sample phase the input capacitor switches
    to the “-” input and the conversion starts (see Figure 8).
    During the conversion, the “+” input voltage is effectively
    “held” by the sample and hold and will not affect the
    conversion result. It is critical that the “–” input voltage be
    free of noise and settle completely during the first CLK
    cycle of the conversion. Minimizing RSOURCE– and C2 will
    improve settling time. If large “–” input source resistance
    must be used the time can be extended by using a slower
    CLK frequency. At the maximum CLK frequency of 1MHz,
    RSOURCE– < 250
    and C2 < 20pF will provide adequate
    settling.
    Input Op Amps
    When driving the analog inputs with an op amp it is
    important that the op amp settles within the allowed time
    (see Figure 8). Again the “+” and “–” input sampling times
    can be extended as described above to accommodate
    slower op amps. Most op amps including the LT1006 and
    LT1013 single supply op amps can be made to settle
    Figure 8. “+” and “–” Input Settling Windows
    DIN
    CLK
    START
    HI-Z
    LTC1293 F08
    CS
    1ST BIT TEST (–) INPUT MUST
    SETTLE DURING THIS TIME
    tSMPL
    (+) INPUT MUST SETTLE DURING THIS TIME
    (+) INPUT
    (–) INPUT
    SGL/
    DIFF
    MSBF
    PS
    DOUT
    B11
    SAMPLE
    HOLD
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