參數(shù)資料
型號(hào)： LTC1292DCN8
廠商： Linear Technology
文件頁(yè)數(shù)： 10/24頁(yè)
文件大小： 0K
描述： IC DATA ACQ SYSTEM 12BIT 8-DIP
標(biāo)準(zhǔn)包裝： 50
類型： 數(shù)據(jù)采集系統(tǒng)（DAS）
分辨率（位）： 12 b
采樣率（每秒）： 60k
數(shù)據(jù)接口： 串行，并聯(lián)
電壓電源： 單電源
電源電壓： 5V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 8-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 8-PDIP
包裝： 管件
18
LTC1292/LTC1297
12927fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figures 17 and 18 show examples of both adequate and
poor settling. Using a slower CLK will allow more time
for the reference to settle. Even at the maximum CLK
rate of 1MHz most references and op amps can be
made to settle within the 1
s bit time. For example the
LT1790 will settle adequately.
Reduced Reference Operation
The effective resolution of the LTC1292/LTC1297 can
be increased by reducing the input span of the con-
verter. The LTC1292/LTC1297 exhibit good linearity
over a range of reference voltages (see typical perfor-
mance characteristics curves of Change in Linearity vs
Reference Voltage). Care must be taken when operat-
ing at low values of VREF because of the reduced LSB
step size and the resulting higher accuracy requirement
placed on the converter. Offset and noise are factors
that must be considered when operating at low VREF
values. The internal reference for VREF has been tied to
the GND pin. Any voltage drop from the GND pin to the
ground plane will cause a gain error.
Offset with Reduced VREF
The offset of the LTC1292/LTC1297 has a larger effect
on the output code when the A/D is operated with a
reduced reference voltage. The offset (which is typi-
cally a fixed voltage) becomes a larger fraction of an
LSB as the size of the LSB is reduced. The typical
performance characteristics curve of Unadjusted Off-
set Error vs Reference Voltage shows how offset in
LSBs is related to reference voltage for a typical value
of VOS. For example a VOS of 0.1mV, which is 0.1LSB
with a 5V reference becomes 0.4LSB with a 1.25V
reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offset-
ting the –IN input to the LTC1292/LTC1297.
Noise with Reduced VREF
The total input referred noise of the LTC1292/LTC1297
can be reduced to approximately 200
VP-P using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This
noise is insignificant with a 5V reference input but will
become a larger fraction of an LSB as the size of the LSB
switching currents due to the switched-capacitor con-
version technique (see Figure 16). During each bit test
of the conversion (every CLK cycle) a capacitive current
spike will be generated on the reference pin by the A/D.
These current spikes settle quickly and do not cause a
problem. If slow settling circuitry is used to drive the
reference input, take care to insure that transients
caused by these current spikes settle completely during
each bit test of the conversion.
RON
8pF TO 40pF
LTC1292
LTC1297
REF+
ROUT
VREF
EVERY
CLK CYCLE
14
13
REF –
LTC1292/7 F16
Figure 16. Reference Input Equivalent Circuit
HORIZONTAL: 1
s/DIV
Figure 17. Adequate Reference Settling (LT1027)
HORIZONTAL: 10
s/DIV
Figure 18. Poor Reference Settling Can Cause A/D Errors
VERTICAL:
0.5mV/DIV
VERTICAL:
0.5mV/DIV
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