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參數(shù)資料
| 型號： | LTC1291CCJ8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-8 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 329K |
| 代理商： | LTC1291CCJ8 |
8
LTC1291
1291fa
U
S
A
O
PPLICATI
WU
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I FOR ATIO
DATA (DIN/DOUT). Data transfer is initiated by a falling chip
select (CS) signal. After CS falls, the LTC1291 looks for a
start bit. After the start bit is received, a 4-bit input word
is shifted into the DIN input which configures the LTC1291
and starts the conversion. After one null bit, the result of
the conversion appears MSB-first on the DOUT line. The
conversion result is output, bit by bit, as the conversion is
performed. At the end of the data exchange, CS should be
brought high. This resets the LTC1291 in preparation for
the next data exchange.
Operating Sequence
(Example: Differential Inputs (CH0+, CH1–))
MSB-FIRST DATA (MSBF = 1)
tCYC
CS
START
MSBF
tSMPL
HI-Z
FILLED WITH ZEROES
B0
B1
DIN
PS
SGL/
DIFF
ODD/
SIGN
DOUT
tCONV
HI-Z
B11
tCONV
B1
B0
B1
B11
FILLED WITH
ZEROES
CLK
DON'T
CARE
LSB-FIRST DATA (MSBF = 0)
tCYC
DON’T
CARE
DON'T CARE
CS
DIN
DOUT
CLK
START
PS
MSBF
ODD/
SIGN
tSMPL
SGL/
DIFF
DON'T CARE
1291 AI03
B11
CS
START
MSBF
HI-Z
FILLED WITH
ZEROES
DIN
PS
SGL/
DIFF
ODD/
SIGN
DOUT
B11
B0
CLK
DON'T CARE
1291 AI04
SHUTDOWN*
NEW CONVERSION BEGINS
START
MSBF
PS
SGL/
DIFF
ODD/
SIGN
HI-Z
DATA NOT VALID
REQUEST POWER SHUTDOWN
* STOPPING THE CLOCK WILL HELP REDUCE POWER CONSUMPTION
CS CAN BE BROUGHT HIGH ONCE DIN HAS BEEN CLOCKED IN
Power Shutdown Operating Sequence
(Example: Differential Inputs (CH0+, CH1–) and MSB-First Data)
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