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參數(shù)資料
| 型號： | LTC1291BIN8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | Single Chip 12-Bit Data Acquisition System |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大小： | 376K |
| 代理商： | LTC1291BIN8 |
12
LTC1291
STAA
$102A
LOAD DUMMY DIN INTO SPI,
START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
D0 GOES HIGH (CS GOES HIGH)
LOAD LTC1291 LSBs IN ACC
STORE LSBs IN $63
WAIT3 LDAA
$1029
WAIT3
$08,X#$01
$102A
$63
BPL
BSET
LDAA
STAA
JMP
LOOP
START NEXT CONVERSION
Interfacing to the Parallel Port of the Intel 8051 Family
The Intel 8051 has been chosen to show the interface
between the LTC1291 and parallel port microprocessors.
Usually the signals CS, D
IN
and CLK are generated on three
port lines and the D
OUT
signal is read on a fourth port line.
LDAA
$1029
WAIT1
$51
$102A
$1029
WAIT2
$102A
$62
$52
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD DIN INTO ACC A FROM $51
LOAD DIN INTO SPI, START SCK
CHECK SPI STATUS REG
CHECK IF TRANSFER IS DONE
LOAD LTC1291 MSBs INTO ACC A
STORE MSBs IN $62
LOAD DUMMY DIN INTO ACC A
FROM $52
WAIT1 BPL
LDAA
STAA
WAIT2 LDAA
BPL
LDAA
STAA
LDAA
LABEL MNEMONIC
OPERAND
COMMENTS
LABEL MNEMONIC
OPERAND
COMMENTS
Timing Diagram for Interface to Intel 8051
Hardware and Software Interface to Intel 8051
LTC1291 AI09
DOUT FROM LTC1291 STORED IN 8051 RAM
MSB
0
0
0
0
B0
B2
B3
B1
B10
B11
LSB
R2
R1
B9
B8
B7
B6
B5
B4
CLK
D
OUT
CS
ANALOG
INPUTS
P1.4
P1.3
8051
D
IN
P1.2
MUX ADDRESS
A/D RESULT
LTC1291
CH0
CH1
This works very well. One can save a line by tying the D
IN
and D
OUT
lines together. The 8051 first sends the start bit
and MUX Address to the LTC1291 over the line connected
to P1.2. Then P1.2 is reconfigured as an input and the 8051
reads back the 12-bit A/D result over the same data line.
CS
CLK
DATA
(D
IN
/D
OUT
)
LTC1291 AI08
1
3
2
4
5
PS BIT LATCHED
INTO LTC1291
8051 P1.2 OUTPUT DATA
TO LTC1291
8051 P1.2 RECONFIGURED
AS INPUT AFTER THE 5TH RISING
CLK BEFORE THE 5TH FALLING CLK
LTC1291 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1291 TAKES CONTROL OF DATA
LINE ON 5TH FALLING CLK
START
B11
SGL/
DIFF
ODD/
SIGN
MSBF
PS
B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
U
S
A
O
PPLICATI
U
U
相關PDF資料 |
PDF描述 |
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| LTC1291BMJ8 | Single Chip 12-Bit Data Acquisition System |
| LTC1291CIN8 | Single Chip 12-Bit Data Acquisition System |
| LTC1291CMJ8 | Single Chip 12-Bit Data Acquisition System |
| LTC1293CCN | Single Chip 12-Bit Data Acquisition System |
| LTC1293BIN | Single Chip 12-Bit Data Acquisition System |
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