RON = 500 LAST SCLK " />

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    參數(shù)資料
    

    


    


    
型號：
LTC1290CCSW#PBF

    

    
廠商：
Linear Technology

    

    
文件頁數(shù)：
13/32頁

    

    
文件大小：
0K

    

    
描述：
IC DATA ACQ SYS 12BIT 20-SOIC

    

    
標準包裝：
38

    

    
類型：
數(shù)據(jù)采集系統(tǒng)（DAS），ADC
    		

    

    
分辨率（位）：
12 b
    		

    

    
采樣率（每秒）：
50k
    		

    

    
數(shù)據(jù)接口：
串行，并聯(lián)
    		

    

    
電壓電源：
雙 ±
    		

    

    
電源電壓：
±5 V，5 V
    		

    

    
工作溫度：
0°C ~ 70°C
    		

    

    
安裝類型：
表面貼裝
    		

    

    
封裝/外殼：
20-SOIC（0.295"，7.50mm 寬）
    		

    

    
供應(yīng)商設(shè)備封裝：
20-SOIC
    		

    

    
包裝：
管件
    		

    

    
產(chǎn)品目錄頁面：
1346 (CN2011-ZH PDF)
    		

    

    

    

	
    
    
    

    
    
	
    20
    LTC1290
    1290fe
    U
    S
    A
    O
    PPLICATI
    WU
    U
    I FOR ATIO
    4TH SCLK
    RON = 500
    LAST SCLK
    CIN =
    100pF
    LTC1290
    “+”
    INPUT
    RSOURCE +
    VIN +
    C1
    “–”
    INPUT
    RSOURCE –
    VIN –
    C2
    LTC1290 F09
    Figure 9. Analog Input Equivalent Circuit
    “+” Input Settling
    This input capacitor is switched onto the “+” input during
    the sample phase (tSMPL, see Figure 10). The sample
    phase starts at the 4th SCLK cycle and lasts until the falling
    edge of the last SCLK (the 8th, 12th or 16th SCLK cycle
    depending on the selected word length). The voltage on
    the “+” input must settle completely within this sample
    time. Minimizing RSOURCE+ and C1 will improve the input
    settling time. If large “+” input source resistance must be
    used, the sample time can be increased by using a slower
    SCLK frequency or selecting a longer word length. With
    the minimum possible sample time of 2
    s, RSOURCE+ < 1k
    and C1 < 20pF will provide adequate settling.
    “–” Input Settling
    At the end of the sample phase the input capacitor switches
    to the “–” input and the conversion starts (see Figure 10).
    During the conversion, the “+” input voltage is effectively
    “held” by the sample-and-hold and will not affect the
    conversion result. However, it is critical that the “–” input
    voltage be free of noise and settle completely during the
    first four ACLK cycles of the conversion time. Minimizing
    RSOURCE– and C2 will improve settling time. If large “–”
    input source resistance must be used, the time allowed for
    settling can be extended by using a slower ACLK fre-
    quency. At the maximum ACLK rate of 4MHz, RSOURCE–
    < 250
     and C2 < 20pF will provide adequate settling.
    Input Op Amps
    When driving the analog inputs with an op amp it is
    important that the op amp settle within the allowed time
    (see Figure 10). Again, the “+” and “–” input sampling
    times can be extended as described above to accommo-
    date slower op amps. Most op amps including the LT1797,
    LT1800 and LT1812 single supply op amps can be made
    to settle well even with the minimum settling windows of
    2
    s (“+” input) and 1s (“–” input) which occur at the
    SCLK
    CS
    “+” INPUT
    ACLK
    1290  F10
    1
    234
      
    MUX ADDRESS
    SHIFTED IN
    tSMPL
    LAST SCLK (8TH, 12TH OR 16TH DEPENDING ON WORD LENGTH)
    1
    234
    1ST BIT TEST
    “–” INPUT MUST SETTLE
    DURING THIS TIME
    SAMPLE
    HOLD
    “+” INPUT
    MUST SETTLE
    DURING THIS TIME
    “–” INPUT
      
    Figure 10. “+” and “–” Input Settling Windows
    
    
    
    
    
    


    


    

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    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
LTC1290CIN
功能描述:IC DATA ACQ SYS 12BIT 20-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS
	Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤

    

    
LTC1290CIN#PBF
功能描述:IC DATA ACQ SYS 12BIT 20-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS
	Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤

    

    
LTC1290CISW
功能描述:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS
	Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤

    

    
LTC1290CISW#PBF
功能描述:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標準包裝:1 系列:- 類型:電機控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1

    

    
LTC1290CISW#PBF
 制造商:Linear Technology 功能描述:ADC, 8CH, 12BIT, 50KSPS, SOIC-20

    

    
    
    
    
	
    	
    
    
     
     
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