previous conversion is output on the DOUT
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� LTC1290CCN
寤犲晢锛� Linear Technology
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 2/32闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC DATA ACQ SYS 12BIT 20-DIP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 18
椤炲瀷锛� 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛�锛孉DC
鍒嗚鲸鐜囷紙浣嶏級锛� 12 b
閲囨ǎ鐜囷紙姣忕锛夛細 50k
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶锛屽苟鑱�(li谩n)
闆诲闆绘簮锛� 闆� ±
闆绘簮闆诲锛� ±5 V锛�5 V
宸ヤ綔婧害锛� 0°C ~ 70°C
瀹夎椤炲瀷锛� 閫氬瓟
灏佽/澶栨锛� 20-DIP锛�0.300"锛�7.62mm锛�
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 20-PDIP
鍖呰锛� 绠′欢
10
LTC1290
1290fe
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
previous conversion is output on the DOUT line. At the end
of the data exchange the requested conversion begins and
CS should be brought high. After tCONV, the conversion is
complete and the results will be available on the next data
transfer cycle. As shown below, the result of a conversion
is delayed by one CS cycle from the input word requesting it.
The LTC1290 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, full duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1290 communicates with microprocessors and
other external circuitry via a synchronous, full duplex,
four-wire serial interface (see Operating Sequence). The
shift clock (SCLK) synchronizes the data transfer with
each bit being transmitted on the falling SCLK edge and
captured on the rising SCLK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex).
Data transfer is initiated by a falling chip select (CS) signal.
After the falling CS is recognized, an 8-bit input word is
shifted into the DIN input which configures the LTC1290
for the next conversion. Simultaneously, the result of the
SGL/
DIFF
SELECT
1
SELECT
0
UNI
MSBF
WL1
MUX ADDRESS
MSB-FIRST/
LSB-FIRST
UNIPOLAR/
BIPOLAR
WORD
LENGTH
LTC1290 AI02
ODD/
SIGN
WL0
DIN
DOUT DOUT WORD 0
DIN WORD 1
DATA
TRANSFER
DOUT WORD 2
DIN WORD 3
DOUT WORD 1
DIN WORD 2
DATA
TRANSFER
tCONV
A/D
CONVERSION
tCONV
A/D
CONVERSION
LTC1290 AI01
Input Data Word
The LTC1290 8-bit data word is clocked into the DIN input
on the first eight rising SCLK edges after chip select is
recognized. Further inputs on the DIN pin are then ignored
until the next CS cycle. The eight bits of the input word are
defined as follows:
123456789
10
11
12
tCONV
tCYC
SHIFT CONFIGURATION
WORD IN
tSMPL
SHIFT A/D RESULT OUT AND
NEW CONFIGURATION WORD IN
B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
(SB)
LTC1290 AI03
SCLK
DIN
DOUT
CS
DON鈥橳 CARE
Operating Sequence
(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
LTC1094ACN#PBF IC DATA ACQ SYS 10BIT 8CH 20-DIP
M83723/75W14047 CONN PLUG 4POS STRAIGHT W/SCKT
VI-B1L-IU-F3 CONVERTER MOD DC/DC 28V 200W
M83723/75W14046 CONN PLUG 4POS STRAIGHT W/SCKT
AD7890BRZ-4REEL IC DAS 12BIT 8CH 24-SOIC
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
LTC1290CCN#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-DIP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Data Converter Basics 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 椤炲瀷:闆绘(j墨)鎺у埗 鍒嗚鲸鐜囷紙浣嶏級:12 b 閲囨ǎ鐜囷紙姣忕锛�:1M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛屽苟鑱�(li谩n) 闆诲闆绘簮:鍠浕婧� 闆绘簮闆诲:2.7 V ~ 3.6 V锛�4.5 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:100-TQFP 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:100-TQFP锛�14x14锛� 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:296-18373-1
LTC1290CCNPBF 鍒堕€犲晢:Linear Technology 鍔熻兘鎻忚堪:ADC SAR 50ksps 12-Bit Serial PDIP20
LTC1290CCSW 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡(p谩n) 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡(p谩n)
LTC1290CCSW#PBF 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 20-SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡(p谩n) 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡(p谩n)
LTC1290CCSW#TR 鍔熻兘鎻忚堪:IC DATA ACQ SYS 12BIT 5V 20SOIC RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - ADCs/DAC - 灏堢敤鍨� 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 椤炲瀷:鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� 鍒嗚鲸鐜囷紙浣嶏級:16 b 閲囨ǎ鐜囷紙姣忕锛�:21.94k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 闆绘簮闆诲:1.8 V ~ 3.6 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:40-WFQFN 瑁搁湶鐒婄洡(p谩n) 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:40-TQFN-EP锛�6x6锛� 鍖呰:鎵樼洡(p谩n)
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�

閲囪臣(g貌u)闇€姹�

(鑻ュ彧閲囪臣(g貌u)涓€姊濆瀷铏�(h脿o)锛屽～瀵�(xi臎)涓€琛屽嵆鍙�)

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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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