參數(shù)資料
型號: LTC1289CCSW#TRPBF
廠商: Linear Technology
文件頁數(shù): 8/28頁
文件大?。?/td> 0K
描述: IC DATA ACQ SYS 12BIT 3V 20-SOIC
標(biāo)準(zhǔn)包裝: 1,000
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 12 b
采樣率(每秒): 25k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 雙 ±
電源電壓: ±3.3V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
16
LTC1289
1289fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 6 shows an example of an ideal ground plane design
for a two-sided board. Of course, this much ground plane
will not always be possible, but users should strive to get
as close to this ideal as possible.
2. Bypassing
For good performance, VCC must be free of noise and
ripple. Any changes in the VCC voltage with respect to
analog ground during a conversion cycle can induce
errors or noise in the output code. VCC noise and ripple can
be kept below 0.5mV by bypassing the VCC pin directly to
the analog ground plane with a 22
F tantalum capacitor
and leads as short as possible. The lead from the device to
the VCC supply should also be kept to a minimum and the
VCC supply should have a low output impedance such as
that obtained from a voltage regulator (e.g., LT1117).
Using a battery to power the LTC1289 will help reduce the
amount of bypass capacitance required on the VCC pin. A
battery placed close to the device will only require 10
F to
adequately bypass the supply pin. Figure 7 shows the
effect of poor VCC bypassing. Figure 8a shows the settling
of a LT1117 low dropout regulator with a 22
F bypass
capacitor. The noise and ripple is approximately 0.5mV.
Figure 8b shows the response of a lithium battery with a 10
F
bypass capacitor. The noise and ripple is kept below 0.5mV.
Figure 7. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors.
Figure 8a. LT1117 Regulator with 22
F Bypassing on VCC
HORIZONTAL: 20
s/DIV
5V/DIV
CS
0.5mV/DIV
VCC
Figure 8b. Lithium Battery with 10
F Bypassing on VCC
HORIZONTAL: 20
s/DIV
Figure 6. Example Ground Plane for the LTC1289
V
22
F
TANTALUM
VCC
LTC1289 AIF06
0.1
F
CERAMIC
DISK
ANALOG
GROUND
PLANE
0.1
F
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
0.5mV/DIV
5V/DIV
CS
VCC
VERTICAL:
0.5mV/DIV
HORIZONTAL: 10
s/DIV
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