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參數(shù)資料
| 型號(hào)： | LTC1289CCSW#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | IC DATA ACQ SYS 12BIT 3V 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 25k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±3.3V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
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18
LTC1289
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A
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PPLICATI
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settling can be extended by using a slower ACLK fre-
quency. At the maximum ACLK rate of 2MHz, RSOURCE– <
200
and C2 < 20pF will provide adequate settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. For single supply low voltage
applications the LT1006, LT1013 and LT1014 can be
made to settle well even with the minimum settling win-
dows of 4
s (“+” input) and 2s (“–” input) which occur
at the maximum clock rates (ACLK = 2MHz and SCLK =
1MHz). Figures 11 and 12 show examples of adequate and
poor op amp settling. The LT1077, LT1078 or LT1079 can
be used here to reduce power consumption. Placing an RC
network at the output of the op amps will improve the
settling response and also reduce the broadband noise.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of CF (e.g., 1F), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately IDC = 100pF × VIN/tCYC and is roughly
proportional to VIN. When running at the minimum cycle
time of 40
s, the input current equals 6.3A at VIN = 2.5V.
In this case, a filter resistor of 10
will cause 0.1LSB of
full-scale error. If a larger filter resistor must be used,
errors can be eliminated by increasing the cycle time as
shown in the typical curve of Maximum Filter Resistor vs
Cycle Time.
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1
A (at 85°C) flowing through a
source resistance of 1k
will cause a voltage drop of 1mV
or 1.6LSB with VREF = 2.5V. This error will be much
reduced at lower temperatures because leakage drops
rapidly (see typical curve of Input Channel Leakage Cur-
rent vs Temperature).
Noise Coupling Into Inputs
High source resistance input signals (>500
) are more
sensitive to coupling from external sources. It is prefer-
able to use channels near the center of the package (i.e.,
CH2-CH7) for signals which have the highest output
resistance because they are essentially shielded by the
HORIZONTAL: 500ns/DIV
Figure 11. Adequate Settling of Op Amps Driving Analog Input
VERTICAL:
5mV/DIV
Figure 13. RC Input Filtering
RFILTER
VIN
CFILTER
LTC1289 AIF13
LTC1289
“+”
“–”
IIDC
HORIZONTAL: 20
s/DIV
Figure 12. Poor Op Amp Settling Can Cause A/D Errors
VERTICAL:
5mV/DIV
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