參數(shù)資料
型號： LTC1288CS8
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages
中文描述： 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： 0.150 INCH, PLASTIC, SO-8
文件頁數(shù)： 22/24頁
文件大小： 412K
代理商： LTC1288CS8
22
LTC1285/LTC1288
D
OUT
FROM 1288 STORED IN 8501 RAM
MSB
R2
B11 B10 B9
LSB
R3
B3
B2
B1 B0 0
B8 B7 B6 B5 B4
0
0
0
TYPICAL APPLICATIO
S
N
Interfacing to the Parallel Port of the INTEL 8051
Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1288 and parallel port micro-
processors. Normally the CS, CLK and D
IN
signals would
be generated on 3 port lines and the D
OUT
signal read on
a 4th port line. This works very well. However, we will
demonstrate here an interface with the D
IN
and D
OUT
of the
LTC1288 tied together as described in the SERIAL INTER-
FACE section. This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1288 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 12-bit A/D result over the same data
line.
U
LABEL
MNEMONIC
MOV
SETB
CLR
MOV
RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
RRC
DJNZ
MOV
SETB
OPERAND
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP 2
R2, A
A
R4, #04
C, P1.2
A
P1.3
P1.3
R4, LOOP 3
R4, #04
A
R4, LOOP 4
R3, A
P1.4
COMMENTS
D
IN
word for LTC1288
Make sure CS is high
CS goes low
Load counter
Rotate D
IN
bit into Carry
SCLK goes low
Output D
IN
bit to LTC1288
SCLK goes high
Next bit
Bit 2 becomes an input
SCLK goes low
Load counter
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
Next bit
Store MSBs in R2
Clear Acc.
Load counter
Read data bit into Carry
Rotate data bit into Acc.
SCLK goes high
SCLK goes low
Next bit
Load counter
Rotate right into Acc.
Next Rotate
Store LSBs in R3
CS goes high
LOOP 1
LOOP 2
LOOP 3
LOOP 4
CS
CLK
D
OUT
D
IN
LTC1288
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
LTC1285/88 TA01
CLK
MSBF BIT LATCHED
INTO LTC1288
8051 P1.2 OUTPUTS DATA
TO LTC1288
LTC1288 SENDS A/D RESULT
BACK TO 8051 P1.2
LTC1288 TAKES CONTROL OF DATA
LINE ON 4TH FALLING CLK
8051 P1.2 RECONFIGURED
AS IN INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
MSBF
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SGL/
DIFF
START
DATA
(
DIN
/D
OUT
)
LTC1285/88 TA07
CS
ODD/
SIGN
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