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參數資料
| 型號： | LTC1287CCJ8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP8 |
| 封裝： | 0.300 INCH, HERMETIC SEALED, CERAMIC, DIP-8 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 315K |
| 代理商： | LTC1287CCJ8 |
LTC1287
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Figures 13 and 14 show examples of both adequate and
poor settling. Using a slower CLK will allow more time
for the reference to settle. Even at the maximum CLK
rate of 500kHz most references and op amps can be
made to settle within the 2
s bit time. For example an
LT1790 with a 4.7
F bypass capacitor will settle
adequately.
Reduced Reference Operation
The effective resolution of the LTC1287 can be in-
creased by reducing the input span of the converter.
The LTC1287 exhibits good linearity over a range of
reference voltages (seeTypical Performance Charac-
teristics curves of Change in Linearity vs Reference
Voltage). Care must be taken when operating at low
values of VREFbecause of the reduced LSB step size and
the resulting higher accuracy requirement placed on
the converter. Offset and Noise are factors that must be
considered when operating at low VREF values.
Offset with Reduced VREF
The offset of the LTC1287 has a larger effect on the
output code when the A/D is operated with a reduced
reference voltage. The offset (which is typically a fixed
voltage) becomes a larger fraction of an LSB as the size
of the LSB is reduced. The Typical Performance Charac-
teristics curve of Unadjusted Offset Error vs Reference
Voltage shows how offset in LSBs is related to reference
voltage for a typical value of VOS. For example a VOS of
0.1mV, which is 0.2LSB with a 2.5V reference becomes
0.4LSB with a 1.25 reference. If this offset is unaccept-
able, it can be corrected digitally by the receiving system
or by offsetting the –IN input to the LTC1287.
Noise with Reduced VREF
The total input referred noise of the LTC1287 can be
reduced to approximately 200
V peak-to-peak using a
ground plane, good bypassing, good layout techniques
and minimizing noise on the reference inputs. This
noise is insignificant with a 2.5V reference input but will
become a larger fraction of an LSB as the size of the LSB
is reduced. The Typical Performance Characteristics
Figure 14. Poor Reference Settling Can Cause A/D Errors
Figure 13. Adequate Reference Settling
HORIZONTAL: 1
s/DIV
VERTICAL:
0.5mV/DIV
VERTICAL:
0.5mV/DIV
HORIZONTAL: 10
s/DIV
conversion (every CLK cycle) a capacitive current spike
will be generated on the reference pin by the A/D. These
current spikes settle quickly and do not cause a prob-
lem. If slow settling circuitry is used to drive the
reference input, take care to insure that transients
caused by these current spikes settle completely during
each bit test of the conversion.
Figure 12. Reference Input Equivalent Circuit
RON
8pF – 40pF
LTC1287
REF+
ROUT
VREF
EVERY CLK CYCLE
14
13
GND
LTC 1287 F12
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