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參數(shù)資料
| 型號(hào)： | LTC1283CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 3V Single Chip 10-Bit Data Acquisition System |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | PLASTIC, SOL-20 |
| 文件頁(yè)數(shù)： | 15/24頁(yè) |
| 文件大?。?/td> | 452K |
| 代理商： | LTC1283CS |
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LTC1283
U
S
A
O
PPLICATI
U
U
Hardware and Software Interface to TI TMS70C42 Processor
Texas Instruments TMS70C42
The TMS70C42 transfers serial data in 8-bit increments,
LSB-first. To accommodate this, the LTC1283 is pro-
grammed for 16-bit word length and LSB-first format. The
10-bit output data is received by the processor as two
8-bit bytes, LSB-first. The LTC1283 fills the final 6 unused
bits (after the MSB) with zeroes.
D
OUT
from LTC1283 stored in TMS70C42 RAM
LABEL
START
MNEMONIC
DINT
MOVP
MOVP
MOV
LDSP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOV
CALL
MOV
MOV
ANDP
MOVP
DESCRIPTION
DISABLES ALL INTERRUPTS
DISABLE INTERRUPT FLAGS
DISABLE INTERRUPT FLAGS
ADDRESS OF STACK
PUT ADDRESS INTO POINTER
CONFIGURE PORT A
ENABLE Tx BY SETTING B3 = 1
RESET THE SERIAL PORT
CONFIGURE THE SERIAL PORT
TURN START BIT OFF
ENABLE THE SERIAL PORT
SET SCLK RATE (TIMER 3)
START TIMER
LOAD D
IN
WORD IN A
ROUTINE THAT SHIFTS DATA
PUT FIRST 8 LSBs IN R5
PUT MSBs IN R6
A0 CLEARED (CS GOES LOW)
PUT D
IN
INTO TXBUF
% > 2A, P0
% > 02, P16
% > 60, B
% > DF, P5
% > 08, P6
% > 40, P21
% > 0C, P20
% > 00, P24
% > 00, P21
% > 00, P23
% > C0, P24
% > DF, A
SXTNBIT
B, R5
A, R6
% > FE, P4
A, P26
LOOP
SXTNBIT
LABEL
MNEMONIC
MOVP
MOVP
MOVP
MOVP
MOV
DJNZ
NOP
MOVP
MOVP
MOVP
MOVP
MOVP
MOVP
MOV
DJNZ
NOP
MOVP
ORP
RETS
DESCRIPTION
SCLK OFF (TIMER 3 DISABLED)
ENABLE SERIAL PORT
SCLK ON (TRANSFER BEGINS)
TXEN GOES LOW
LOAD COUNTER
LOOP WHILE SHIFT OCCURS
DELAY
PUT D
OUT
IN B
LOAD TXBUF
SCLK OFF (TIMER 3 DISABLE)
ENABLE SERIAL PORT
SCLK ON (TRANSFER BEGINS)
TXEN GOES LOW
LOAD COUNTER
LOOP WHILE SHIFT OCCURS
DELAY
PUT D
OUT
IN A
A0 SET (CS GOES HIGH)
RETURN TO MAIN PROGRAM
% > 40, P24
% > 17, P21
% > C0, P24
% > 16, P21
% > 02, A
A, WAIT1
WAIT1
P25, B
A, P26
% > 40, P24
% > 17, P21
% > C0, P24
% > 16, P21
% > 02, A
A, WAIT2
WAIT2
P25, A
% > 01, P4
Signetics 83CL410
To interface to the 83CL410, (a 3V version of the 80C51)
the LTC1283 is programmed for MSB-first format and 10-
bit word length. The 83CL410 generates CS, SCLK and D
IN
on three port lines and reads D
OUT
on the fourth.
Parallel Port Microprocessors
When interfacing the LTC1283 to an MPU which has a
parallel port, the serial signals are created on the port with
software. Three MPU port lines are programmed to create
the CS, SCLK and D
IN
signals for the LTC1283. A fourth
port line reads the D
OUT
line. An example is made of the
Signetics 83CL410.
Hardware and Software Interface to Signetics 83CL410 Processor
D
OUT
D
IN
SCLK
CS
ACLK
P1.1
P1.2
P1.3
P1.4
ALE
ANALOG
INPUTS
LTC1283
83CL410
LTC1283 AI17
CS
SCLK
D
IN
D
OUT
AO
SCLK
T
XD
R
XD
LTC1283
TMS70C42
LTC1283 AI15
ANALOG
INPUTS
7
6
5
4
3
2
1
0
LSB
FILL WITH ZEROES
BYTE 1
LTC1283 AI16
0
0
0
0
0
0
9
8
BYTE 2
MSB
D
OUT
from LTC1283 stored in 83CL410 RAM
B9
B8
B7
B6
B5
B4
B3
B2
MSB*
LSB
LTC1283 AI18
B1
B2
0
0
0
0
0
0
R2
R3
*B9 IS MSB IN UNIPOLAR OR
SIGN BIT IN BIPOLAR
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| LTC1283 | 3V Single Chip 10-Bit Data Acquisition System(3V，單片，10位數(shù)據(jù)采集系統(tǒng)) |
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