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參數(shù)資料
| 型號(hào)： | LTC1283ACN#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | LEAD FREE, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 338K |
| 代理商： | LTC1283ACN#TRPBF |
14
LTC1283
1283fb
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
CS
SCLK
DIN
DOUT
G1
SK
SO
SI
ANALOG
INPUTS
LTC1283
COP820C
LTC1283 AI11
Motorola SPI (MC68HC05C4, MC68HC11)
The MC68HC05C4 and MC68HC11 transfer data MSB-
first and in 8-bit increments. Programming the LTC1283
for MSB-first format and 16-bit word length allows the 10-
bit data output to be received by the MPU as two 8-bit
bytes with the final 6 unused bits filled with zeroes by the
LTC1283.
B9
B8
B7
B6
B5
B4
B3
B2
MSB*
LSB
*B9 is MSB in unipolar or sign bit in bipolar
BYTE 1
LTC1283 AI14
B1
B0
0
BYTE 2
LOCATION A
LOCATION A + 1
MNEMONIC
COMMENTS
BCLR n
C0 IS CLEARED (CS GOES LOW)
LDA
LOAD DIN FOR LTC1283 INTO ACC
STA
LOAD DIN FROM ACC TO SPI DATA REG. START SCK
↑
NOP
8 NOPs FOR TIMING
↓
LDA
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LDA
LOAD LTC1283 DOUT FROM SPI DATA REG.
INTO ACC (BYTE 1)
STA
LOAD LTC1283 DOUT INTO RAM (LOCATION A)
MNEMONIC
COMMENTS
STA
START NEXT SPI CYCLE
↑
NOP
6 NOPs FOR TIMING
↓
BSET n
CO IS SET (CS GOES HIGH)
LDA
LOAD CONTENTS OF SPI STATUS REG. INTO ACC
LDA
LOAD LTC1283 DOUT FROM SPI DATA REG.
INT ACC (BYTE 2)
STA
LOAD LTC1283 INTO RAM (LOCATION A +1)
Hardware and Software Interface to Motorola MC68HC05C4 and
MC68HC11 Processors
DOUT from LTC1283 stored in MC68HC05C4 or MC68HC11 RAM
98
7
6
5
4
3
2
MSB*
LSB
*B9 is MSB in unipolar or sign bit in bipolar
BYTE 1
LTC1283 AI12
10X
X
BYTE 2
Hardware and Software Interface to National Semiconductor
COP820C Processor
DOUT from LTC1283 stored in COP820C RAM
MNEMONIC
COMMENTS
LD (F0)
←0D
LOAD 0D INTO F0 (DIN)
LD (D5)
←32
CONFIGURE PORT G
LD (EE)
←8
CONFIGURE CONTROL REG.
LD (B)
←D4
PORT G DATA REG. INTO B
LD (A)
←(F0)
LOAD DIN INTO ACC
RBIT 1
G1 RESET (CS GOES LOW)
X (A)
←→(E9)
LOAD DIN INTO SHIFT REG.
LD (B)
←EF
LOAD PSW REG. ADDR IN B
SBIT 2
TRANSFER BEGINS
↑
NOP
15 NOPs FOR TIMING
↓
MNEMONIC
COMMENTS
X(A)
←→(E9)
LOAD DOUT INTO ACC
SBIT 2
TRANSFER CONTINUES
X (A)
←→(F3)
LOAD DOUT IN ADDR F3
RBIT 2
STOP TRANSFER
LD (B)
←D4
PUT PORT G ADDR IN B
SBIT 1
G1 SET (CS GOES HIGH)
X (A)
←→(E9)
LOAD DOUT INTO ACC
RC
CLEAR CARRY
RRCA
SHIFT RIGHT THRU CARRY
RRCA
SHIFT RIGHT THRU CARRY
RRCA
SHIFT RIGHT THRU CARRY
X (A)
←→(F4)
LOAD DOUT IN ADDR F4
CS
SCLK
DIN
DOUT
C0
SCK
MOSI
MISO
ANALOG
INPUTS
LTC1283
MC68HC05C4
MC68HC11
LTC1283 AI13
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