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參數(shù)資料
| 型號： | LTC1277 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 12-Bit, 10mW, 100ksps ADCs with 1mA Shutdown(10mW, 100ksps，12位A/D轉(zhuǎn)換器（帶1mA關(guān)斷）) |
| 中文描述： | 12位，僅為10mW，100ksps的與1mA的關(guān)斷（僅為10mW，100ksps的12位模數(shù)轉(zhuǎn)換器的A / D轉(zhuǎn)換器（帶1mA的關(guān)斷）） |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 349K |
| 代理商： | LTC1277 |
19
LTC1274/LTC1277
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
S
A
O
PPLICATI
IU
U
The LTC1277 has an additional Nap mode. When NAP
(Pin 7) is tied low, all the power is off except the internal
reference which is still active and provides 2.42V output
voltage to the other circuitry. In this mode the ADC draws
0.9mW instead of 10mW (for minimum power, the logic
inputs must be within 600mV from the supply rails). The
wake-up time from the power shutdown to active state is
620ns. The typical performance graph on the front page of
this data sheet shows that the power will be reduced
greatly by using the Sleep and Nap modes.
Power Shutdown
The LTC1274/LTC1277 provide shutdown features that
will save power when the ADC is in inactive periods. Both
ADCs have a Sleep mode. To power down the ADCs,
SLEEP (Pin 18 in LTC1274 or Pin 6 in LTC1277) needs to
be driver low.
When in Sleep mode, the LTC1274/LTC1277
will not start a conversion even though the CONVST goes
low. The parts draw 1
μ
A. After release from the Sleep
mode, the ADCs need 3ms (4.7
μ
F bypass capacitor on
V
REF
pin) to wake up and a REFRDY signal will go to high
to indicate the ADC is ready to do conversions.
RD = CONVST
BUSY
LTC1274/77 F16
t
15
t
18
CS = 0
HBEN (LTC1277)
DATA N
DB11 TO DB0
DATA N
DB7 TO DB0
DATA (N – 1)
DB7 TO DB0
DATA (N – 1)
DB11 TO DB0
DATA N
DB11 TO DB8
LTC1274 DATA
LTC1277 DATA
t
5
t
9
t
6
t
10
t
7
(SAMPLE N)
DATA (N + 1)
DB7 TO DB0
DATA N
DB11 TO DB0
DATA (N + 1)
DB11 TO DB8
(SAMPLE N + 1)
DATA (N + 1)
DB11 TO DB0
DATA N
DB11 TO DB0
t
CONV
Figure 16. Slow Memory Mode
RD = CONVST
BUSY
LTC1274/77 F17
t
15
CS = 0
HBEN (LTC1277)
DATA (N – 1)
DB11 TO DB0
DATA (N – 1)
DB7 TO DB0
DATA (N – 1)
DB11 TO DB8
LTC1274 DATA
LTC1277 DATA
t
5
t
18
t
9
t
10
t
7
(SAMPLE N)
DATA N
DB7 TO DB0
DATA N
DB11 TO DB8
(SAMPLE N + 1)
DATA N
DB11 TO DB0
t
CONV
Figure 17. ROM Mode Timing
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