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參數(shù)資料
| 型號： | LTC1257CS8#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT VOLT OUT SGL 8SOIC |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.75mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
LTC1257
6
1257fc
PIN FUNCTIONS
DEFINITIONS
VOUT (Pin 7): The buffered DAC output is capable of
sourcing 2mA over temperature while pulling within 2.7V
of VCC. The output will pull to ground through an internal
250Ω equivalent resistance.
VCC (Pin 8): The positive supply input. 4.75V ≤ VCC ≤
15.75V. Requires a bypass capacitor to ground.
LSB: The least significant bit or the ideal voltage difference
between two successive codes.
LSB = (VFS – VOS)/2n – 1
n
= The number of digital input bits
VOS = The zero code error or offset of the DAC
VFS = The full-scale output voltage of the DAC
measured when all bits are set to 1
Resolution: The resolution is the number of DAC output
states (2n) that divide the full-scale range. The resolution
does not imply linearity.
INL:End-pointintegralnonlinearityisthemaximumdevia-
tion from a straight line passing through the end-points of
the DAC transfer curve. Because the part operates from
a single supply and the output cannot go below ground,
the linearity is measured between full-scale and the first
code that guarantees a positive output. The INL error at
a given input code is calculated as follows:
INL
= (VOUT – VIDEAL)/LSB
VIDEAL = (Code)(LSB) + VOS
VOUT = The output voltage of the DAC measured at
the given input code
DNL: Differential nonlinearity is the difference between
the measured change and the ideal 1LSB change between
any two adjacent codes. The DNL error between any two
codes is calculated as follows:
DNL = (VOUT – LSB)/LSB
VOUT= The measured voltage difference between two
adjacent codes
Offset Error: The theoretical voltage at the output when
the DAC is loaded with all zeros. The output amplifier can
have a true negative offset, but because the part is oper-
ated from a single supply, the output cannot go below
ground. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
The offset of the part is measured at the first code that
produces an output voltage 0.5LSB greater than the
previous code:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
Full-Scale Error: Full-scale error is the difference between
the ideal and measured DAC output voltages with all bits
set to one (Code = 4095). The full-scale error includes the
offset error and is calculated as follows:
FSE = (VOUT – VIDEAL)/LSB
VIDEAL = (VREF)(1 – 2–n) – VOS
VREF =Thereferencevoltage,eitherinternalorexternal
Gain Error: Gain error is the difference between the ideal
and measured slope of the DAC transfer characteristic.
Gain error is equal to full-scale error minus offset error.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
{
DAC CODE
0V
1257 F01
Figure 1. Effect of Negative Offset
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