參數(shù)資料
型號(hào)： LTC1094CN#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ SYS 10BIT 8CH 20-DIP
標(biāo)準(zhǔn)包裝： 18
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 10 b
數(shù)據(jù)接口： 串行
電壓電源： 雙 ±
電源電壓： ±5V，4.5V，10V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 20-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 20-PDIP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1345 (CN2011-ZH PDF)
21
LTC1091/LTC1092
LTC1093/LTC1094
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
3. Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1091/
LTC1092/LTC1093/LTC1094 have capacitive switching
input current spikes. These current spikes settle quickly
and do not cause a problem. However, if large source
resistances are used or if slow settling op amps drive the
inputs, care must be taken to ensure that the transients
caused by the current spikes settle completely before the
conversion begins.
Source Resistance
The analog inputs of the LTC1091/LTC1092/LTC1093/
LTC1094 look like a 60pF capacitor (CIN) in series with a
500
resistor (RON) as shown in Figure 7. CIN gets
switched between the selected “+” and “–” inputs once
during each conversion cycle. Large external source resis-
tors and capacitances will slow the settling of the inputs. It
is important that the overall RC time constants be short
enough to allow the analog inputs to completely settle
within the allowed time.
“+” Input Settling
This input capacitor is switched onto the “+” input during
the sample phase (tSMPL, see Figure 8). The sample phase
is the 1 1/2 CLK cycles before the conversion starts. The
voltage on the “+” input must settle completely within this
sample time. Minimizing RSOURCE+ and C1 will improve
the input settling time. If large “+” input source resistance
must be used, the sample time can be increased by using
a slower CLK frequency. With the minimum possible
sample time of 3
s, RSOURCE+ < 2k and C1 < 20pF will
provide adequate settling.
Figure 5. Poor VCC Bypassing.
Noise and Ripple Can Cause A/D Errors
10
s/DIV
1091-4 F05
0.5mV/DIV
Figure 6. Good VCC Bypassing Keeps
Noise and Ripple on VCC Below 1mV
0.5mV/DIV
10
s/DIV
1091-4 F06
3RD CLK
↑
RON = 500
4TH CLK
↓
CIN =
60pF
LTC1091
“+”
INPUT
RSOURCE+
VIN+
C1
“–”
INPUT
RSOURCE–
VIN–
C2
LTC091-4 F07
Figure 7. Analog Input Equivalent Circuit
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