參數(shù)資料
型號(hào)： LTC1091CN8
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 1-, 2-, 6- and 8-Channel, 10-Bit Serial I/O Data Acquisition Systems
中文描述： 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8
封裝： PLASTIC, DIP-8
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 356K
代理商： LTC1091CN8
18
LTC 1091/LTC 1092
LTC 1093/LTC 1094
U
S
A
Motorola SPI (MC68HC05C4, MC68HC11)
O
PPLICATI
W
U
I FOR ATIO
U
Hardware and Software Interface to
Motorola MC68HC05C4 Processor
The MC68HC05C4 has been chosen as an example of an
MPU with a dedicated serial port. This MPU transfers data
MSB first and in 8-bit increments. With two 8-bit transfers,
the A/D result is read into the MPU. The first 8-bit transfer
sends the D
IN
word to the LTC1091 and clocks B9 and B8
of the A/D conversion result into the processor. The
second 8-bit transfer clocks the remaining bits, B7 through
B0, into the MPU.
ANDing the first MPU received byte with 03 Hex clears the
six most significant bits. Notice how the position of the
start bit in the first MPU transmit word is used to position
the A/D result right justified in two memory locations.
X = DON’T CARE
1091/2/3/4 AI15
CLK
CS
D
OUT
MPU RECEIVED
WORD
MPU TRANSMIT
WORD
START
BIT
BYTE 1
D
IN
START
MSBF
MSBF X X X
B9
0
B9
B8
B8
B7
B6
B5
B4
B3
B2
B1
B0
SGL/
DIFF
ODD/
SIGN
SGL/
DIFF
ODD/
SIGN
0 1
BYTE 2 (DUMMY)
X X X
X X X
X X
BYTE 1
1ST TRANSFER
BYTE 2
B5 B4 B3
B2 B1 B0
B7 B6
DON’T CARE
2ND TRANSFER
Data Exchange Between LTC1091 and MC68HC05C4
1091-4 AI16
BYTE 1
0 0 0 0 0 0 B9 B8
D
OUT
from LTC1091 Stored in MC68HC05C4 RAM
MSB
LOCATION A
B7 B6 B5 B4 B3 B2 B1 B0
LSB
LOCATION A + 1
BYTE 2
LTC1091
CS
CLK
DIN
DOUT
ANALOG
INPUTS
CO
SCK
MOSI
MISO
MC68HC05C4
LABEL
START
MNEMONIC
BCLRn
LDA
STA
COMMENTS
Bit 0 Port C Goes Low (CS Goes Low)
Load LTC1090 D
IN
Word into Acc
Load LTC1090 D
IN
Word into SPI from Acc
Transfer Begins
Test Status of SPIF
Loop to Previous Instruction If Not Done
with Transfer
Load contents of SPI Data Register into
Acc (D
OUT
MSBs)
Start Next SPI Cycle
Clear 6 MSBs of First D
OUT
Word
Store in Memory Location A (MSBs)
Test Status of SPIF
Loop to Previous Instruction If Not Done
with Transfer
Set B0 of Port C (CS Goes High)
Load contents of SPI Data Register into
Acc (D
OUT
LSBs)
Store in Memory location A + 1 (LSBs)
TST
BPL
LDA
STA
AND
STA
TST
BPL
BSETn
LDA
STA
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