參數(shù)資料
型號(hào)： LTC1091CN8#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC DATA ACQ SYS 10BIT 2CH 8-DIP
標(biāo)準(zhǔn)包裝： 50
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 10 b
數(shù)據(jù)接口： 串行
電壓電源： 雙 ±
電源電壓： ±5V，4.5V，10V
工作溫度： -40°C ~ 85°C
安裝類型： 通孔
封裝/外殼： 8-DIP（0.300"，7.62mm）
供應(yīng)商設(shè)備封裝： 8-PDIP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1345 (CN2011-ZH PDF)
23
LTC1091/LTC1092
LTC1093/LTC1094
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
Figure 9. Adequate Settling of Op Amp Driving Analog Input
5mV/DIV
1
s/DIV
1091-4 F09
5mV/DIV
20
s/DIV
1091-4 F10
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 11. For large values of CF (e.g., 1F), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a small
resistor and large capacitor to prevent DC drops across the
resistor. The magnitude of the DC current is approximately
IDC = (60pF)(VIN/tCYC) and is roughly proportional to VIN.
When running at the minimum cycle time of 32
s, the input
current equals 9
A at VIN = 5V. In this case, a filter resistor
of 50
will cause 0.1LSB of full-scale error. If a larger filter
resistor must be used, errors can be eliminated by increas-
ing the cycle time as shown in the typical curve of Maximum
Filter Resistor vs Cycle Time.
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1
A (at 125°C) flowing through a
source resistance of 1k
will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see the
typical curve of Input Channel Leakage Current vs
Temperature).
4. Sample-and-Hold
Single-Ended Inputs
The LTC1091/LTC1093/LTC1094 provide a built-in sample-
and-hold (S&H) function for all signals acquired in the single-
ended mode. This sample-and-hold allows conversion of
rapidly varying signals (see typical curve of S&H Acquisition
Time vs Source Resistance). The input voltage is sampled
during the tSMPL time as shown in Figure 8. The sampling
interval begins as the bit preceding the MSBF bit is shifted in
and continues until the falling CLK edge after the MSBF bit is
received. On this falling edge, the S&H goes into hold mode
and the conversion begins.
Figure 11. RC Input Filtering
RFILTER
VIN
CFILTER
1091-4 F11
LTC1091
“+”
“–”
IDC
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