參數(shù)資料
型號: LTC1091
廠商: Linear Technology Corporation
英文描述: 2-Channel, 10-Bit I/O Data Acquisition Systems(雙通道,10位,串行I/O數(shù)據(jù)采集系統(tǒng))
中文描述: 2通道,10位I / O數(shù)據(jù)采集系統(tǒng)(雙通道,10位,串行的I / O數(shù)據(jù)采集系統(tǒng))
文件頁數(shù): 19/32頁
文件大?。?/td> 277K
代理商: LTC1091
19
LTC 1091/LTC 1092
LTC 1093/LTC 1094
U
S
A
O
PPLICATI
W
U
I FOR ATIO
U
Interfacing to the Parallel Port of the
Intel 8051 Family
The Intel 8051 has been chosen to demonstrate the
interface between the LTC1091 and parallel port micro-
processors. Normally, the CS, SCLK and D
IN
signals
would be generated on three port lines and the D
OUT
signal
read on a 4th port line. This works very well. However, we
will demonstrate here an interface with the D
IN
and D
OUT
of the LTC1091 tied together as described in section 4.
This saves one wire.
The 8051 first sends the start bit and MUX address to the
LTC1091 over the data line connected to P1.2. Then P1.2
is reconfigured as an input (by writing to it a one) and the
8051 reads back the 10-bit A/D result over the same data
line.
1091-4 AI17
LTC1091
CS
CLK
DOUT
DIN
ANALOG
INPUTS
P1.4
P1.3
P1.2
8051
MUX ADDRESS
A/D RESULT
B9 B8 B7 B6 B5 B4 B3 B2
D
OUT
from LTC1091 Stored in 8051 RAM
MSB
R2
B1 B0 0 0 0 0 0 0
LSB
R3
LABEL
MNEMONIC
MOV
SETB
CLR
MOV
OPERAND
A, #FFH
P1.4
P1.4
R4, #04
A
P1.3
P1.2, C
P1.3
R4, LOOP 1
P1, #04
P1.3
R4, #09
C, P1.2
A
P1.3
P1.3
R4, LOOP
R2, A
C, P1.2
P1.3
P1.3
A
A
C, P1.2
A
A
R3, A
P1.4
COMMENTS
D
IN
Word for LTC1091
Make Sure CS Is High
CS Goes Low
Load Counter
Rotate D
IN
Bit into Carry
SCLK Goes Low
Output D
IN
Bit to LTC1091
SCLK Goes High
Next Bit
Bit 2 Becomes an Input
SCLK Goes Low
Load Counter
Read Data Bit into Carry
Rotate Data Bit into Acc
SCLK Goes High
SCLK Goes Low
Next Bit
Store MSBs in R2
Read Data Bit into Carry
SCLK Goes High
SCLK Goes Low
Clear Acc
Rotate Data Bit from Carry to Acc
Read Data Bit into Carry
Rotate Right into Acc
Rotate Right into Acc
Store LSBs in R3
CS Goes High
LOOP 1 RLC
CLR
MOV
SETB
DJNZ
MOV
CLR
MOV
MOV
RLC
SETB
CLR
DJNZ
MOV
MOV
SETB
CLR
CLR
RLC
MOV
RRC
RRC
MOV
SETB
LOOP
1091/2/3/4 AI18
CLK
START
MSBF
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
8051 P1.2 RECONFIGURED AS AN
INPUT AFTER THE 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
8051 P1.2 OUTPUTS
DATA TO LTC1091
LTC1091 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
SGL/
DIFF
ODD/
SIGN
CS
DATA (D
IN
/D
OUT
)
1
2
MSBF BIT
LATCHED
INTO LTC1091
3
4
LTC1091 SENDS A/D RESULT
BACK TO 8051 P1.2
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