參數(shù)資料
型號(hào): LTC1090CN#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 25/28頁(yè)
文件大小: 0K
描述: IC DATA ACQUIS SYS 10BIT 20-DIP
標(biāo)準(zhǔn)包裝: 18
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 10 b
采樣率(每秒): 30k
數(shù)據(jù)接口: 串行
電壓電源: 單/雙電源
電源電壓: ±5V,5V,10V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 20-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1345 (CN2011-ZH PDF)
6
LTC1090
1090fc
UU
U
PI FU CTIO S
#
PIN
FUNCTION
DESCRIPTION
1-8
CH0 to CH7
Analog Inputs
The analog inputs must be free of noise with respect to AGND.
9
COM
Common
The common pin defines the zero reference point for all single ended inputs. It must be free
of noise and is usually tied to the analog ground plane.
10
DGND
Digital Ground
This is the ground for the internal logic. Tie to the ground plane.
11
AGND
Analog Ground
AGND should be tied directly to the analog ground plane.
12
V
Negative Supply
Tie Vto most negative potential in the circuit. (Ground in single supply applications.)
13,14
REF , REF+
Reference Inputs
The reference inputs must be kept free of noise with respect to AGND.
15
CS
Chip Select Input
A logic low on this input enables data transfer.
16
DOUT
Digital Data Output
The A/D conversion result is shifted out of this output.
17
DIN
Data Input
The A/D configuration word is shifted into this input.
18
SCLK
Shift Clock
This clock synchronizes the serial data transfer.
19
ACLK
A/D Conversion Clock
This clock controls the A/D conversion process.
20
VCC
Positive Supply
This supply must be kept free of noise and ripple by bypassing directly to the analog ground
plane.
BLOCK DIAGRA
W
DIN
17
DOUT
16
SCLK
18
LTC1090 BD01
CH0
1
CH1
2
CH2
3
CH3
4
CH4
5
CH5
6
CH6
7
CH7
8
COM
9
VCC
20
INPUT SHIFT
REGISTER
OUTPUT
SHIFT
REGISTER
CS
15
ACLK
19
CONTROL
AND
TIMING
10-BIT
SAR
SAMPLE
AND HOLD
ANALOG
INPUT
MUX
COMP
REF –
13
10-BIT
CAPACITIVE
DAC
REF+
V–
12
AGND
11
DGND
10
14
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