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參數(shù)資料
| 型號： | LTC1067IS#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC FILTR BLD BLK DUAL R-R 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 濾波器類型： | 通用開關(guān)電容器 |
| 頻率 - 截止或中心： | 20kHz |
| 濾波器數(shù)： | 2 |
| 濾波器階數(shù)： | 4th |
| 電源電壓： | 3 V ~ 11 V，±3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
12
LTC1067/LTC1067-50
APPLICATIONS INFORMATION
WU
U
A switched-capacitor integrator generally exhibits a higher
input offset than a discrete RC integrator. The larger offset
is mainly due to the charge injection from the CMOS
switches into the integrated capacitor. The integrator’s op
amp offset, typically a couple of millivolts, also adds to the
overall offset value. Figure 9 shows the input offsets from
a single 2nd order section. Table 2 lists the formula for the
output offset voltage for various modes and output pins.
+
–
HP/N
BP
+
–
LP
∑ V
OS2
VOS3
1067 F09
VOS1
INV
S
Table 2. Output DC Offsets for a Second Order Section
MODE
VOSHP/N
VOSBP
VOSLP
1VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3)
VOS3
VOSHP/N – VOS2
1b
VOS1 [1 + (R2/R3) + (R2/R1)] – (VOS3)(R2/R3)
VOS3
(VOSHP/N – VOS2)[1 + (R5/R6)]
2VOS1 [1 + (R2/R3) + (R2/R1) + (R2/R4) – (VOS3)VOS3
VOSHP/N – VOS2
(R2/R3)](R4/R2 + R4) + (VOS2)(R2/R2 + R4)
3VOS2
VOS3
VOS1 [1 + (R4/R1) + (R4/R2) + (R4/R3)] – (VOS2)
(R4/R2) – (VOS3)(R4/R3)
limits defined by the Typical Performance Characteristics
graphs, passband gain variations of 2dB or more should be
expected.
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pins. The clock feedthrough is tested with the
filter’s input grounded and depends on PC board layout
and on the value of the power supplies. With proper layout
techniques, the typical values of clock feedthrough are
listed under Electrical Characteristics.
Any parasitic switching transients during the rising and
falling edges of the incoming clock are not part of the clock
feedthrough specifications. Switching transients have fre-
quency contents much higher than the applied clock; their
amplitude strongly depends on scope probing techniques
as well as grounding and power supply bypassing. The
clock feedthrough, can be greatly reduced by adding a
simple RC lowpass network at the final filter output. This
RC will completely eliminate any switching transients.
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to deter-
mine the operating signal-to-noise ratio. Most of its fre-
quency contents lie within the filter passband and cannot
be reduced with post filtering. For a notch filter the noise
of the filter is centered at the notch frequency.
The total wideband noise (
VRMS)isnearlyindependentof
the value of the clock. The clock feedthrough specifica-
tions are not part of the wideband noise.
For a specific filter design, the total noise depends on the
Q of each section and the cascade sequence.
Operating Limits
The Maximum Q vs Frequency (fO) graphs, under Typical
Performance Characteristics, define an upper limit of
operating Q for each LTC1067 (or LTC1067-50) 2nd order
section. These graphs indicate the power supply, fO and Q
value conditions under which a filter implemented with an
LTC1067 will remain stable when operated at tempera-
tures of 70
°C or less. For a 2nd order section, a bandpass
gain error of 3dB or less is arbitrarily defined as a condition
for stability.
When the passband gain error begins to exceed 1dB, the use
of capacitor CC will reduce the gain error (capacitor CC is
connected from the lowpass node to the inverting node of a
2nd order section). Please refer to Figures 3 through 8. The
value of CC can be best determined experimentally, and as a
guide it should be about 5pF for each 1dB of gain error and
not to exceed 15pF. When operating the LTC1067 near the
Figure 9. Block Diagram of a 2nd Order Section
Showing the Input Offsets
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