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參數(shù)資料
| 型號： | LTC1064CSW |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTR BUILDNG BLK QUAD 24SOIC |
| 標準包裝： | 32 |
| 濾波器類型： | 通用開關電容器 |
| 頻率 - 截止或中心： | 140kHz |
| 濾波器數(shù)： | 4 |
| 濾波器階數(shù)： | 8th |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 24-SOIC |
| 包裝： | 管件 |
| 其它名稱： | LTC1064CS |
LTC1064
7
1064fb
ANALOG
GROUND
PLANE
NOTE: CONNECT ANALOG AND DIGITAL
GROUND PLANES AT A SINGLE POINT AT
THE BOARD EDGE
FOR BEST HIGH FREQUENCY RESPONSE
PLACE RESISTORS PARALLEL TO DOUBLE-
SIDED COPPER CLAD BOARD AND LAY FLAT
(4 RESISTORS SHOWN HERE TYPICAL)
LTC1064
0.1
F
CERAMIC
PIN 1 IDENT
1064 F02
5k
–7.5V
7.5V
0.1
F CERAMIC
(SINGLE POINT
GROUND)
CLOCK
VIN
1
2
3
4
5
6
7
8
9
10
11
12
DIGITAL
GROUND
PLANE
24
23
22
21
20
19
18
17
16
15
14
13
APPLICATIONS INFORMATION
WU
U
Figure 2. Example Ground Plane Breadboard Technique for LTC1064
ANALOG CONSIDERATIONS
Grounding and Bypassing
The LTC1064 should be used with separated analog and
digital ground planes and single point grounding
techniques.
Pin 6 (AGND) should be tied directly to the analog ground
plane.
Pin 7 (V +) should be bypassed to the ground plane with a
0.1
F ceramic capacitor with leads as short as possible.
Pin 19 (V –) should be bypassed with a 0.1
F ceramic
capacitor. For single supply applications, V – can be tied to
the analog ground plane.
For good noise performance, V + and V – must be free of
noise and ripple.
All analog inputs should be referenced directly to the
single point ground. The clock inputs should be shielded
from and/or routed away from the analog circuitry and a
separate digital ground plane used.
Figure 2 shows an example of an ideal ground plane
design for a 2-sided board. Of course this much ground
plane will not always be possible, but users should strive
to get as close to this as possible. Protoboards are not
recommended.
Buffering the Filter Output
When driving coaxial cables and 1
× scope probes, the
filter output should be buffered. This is important espe-
cially when high Qs are used to design a specific filter.
Inadequate buffering may cause errors in noise, distor-
tion, Q and gain measurements. When 10
× probes are
used, buffering is usually not required. An inverting buffer
is recommended especially when THD tests are per-
formed. As shown in Figure 3, the buffer should be
adequately bypassed to minimize clock feedthrough.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1064-CSW | 制造商:LINEAR TECH 功能描述:_ |
| LTC1064CSW#PBF | 功能描述:IC FILTR BUILDNG BLK QUAD 24SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 濾波器類型:連續(xù)時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) |
| LTC1064CSW#PBF | 制造商:Linear Technology 功能描述:FILTER, LOW PASS, 50KHZ, SOIC-24 |
| LTC1064CSW#TR | 功能描述:IC FILTER LP BLD BLK QUAD 24SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 濾波器類型:連續(xù)時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) |
| LTC1064CSW#TRPBF | 功能描述:IC FILTR BUILDNG BLK QUAD 24SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 濾波器類型:連續(xù)時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) |
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