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參數(shù)資料
| 型號： | LTC1064-4CSW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FILTR 8TH ORDR LOWPASS 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 濾波器類型： | 考爾，低通開關(guān)電容器 |
| 頻率 - 截止或中心： | 100kHz |
| 濾波器數(shù)： | 1 |
| 濾波器階數(shù)： | 8th |
| 電源電壓： | ±2.37 V ~ 8 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1324 (CN2011-ZH PDF) |
LTC1064-4
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PI FU CTIO S
INV C, COMP1, INV A, COMP2 (Pins 1, 6, 7 and 13): To
obtain a Cauer response with minimum passband ripple
and cutoff frequencies above 20kHz, compensating com-
ponents are required. Figure 6 uses ±7.5V power supplies
and compensation components to achieve up to 40kHz
sweepable cutoff frequencies and ±0.1dBpassbandripple.
Table 7 lists the typical amplitude response of Figure 6.
Figure 7 illustrates the compensation scheme required to
obtain a 100kHz cutoff frequency; Graph 4 and Tables 8
and 9 list the typical response of Figure 7 for 25°C and
125°C ambient temperature. As shown the ripple in-
creases at high temperatures but still a ±0.25dB figure
can be obtained for ambient temperatures below 70°C.
VIN, VOUT (Pins 2, 9): The input Pin 2 is connected to a 12k
resistor tied to the inverting input of an op amp. Pin 2 is
protected against static discharge. The device’s output,
Pin 9, is the output of an op amp which can typically
source/sink 3mA/1mA. Although the internal op amps are
unity gain stable, driving long coax cables is not recom-
mended.
When testing the device for noise and distortion, the
output, Pin 9, should be buffered (Figure 4).
The op amp
power supply wire (or trace) should be connected
directly to the power source. To eliminate any output
clock feedthrough, Pin 9 should be buffered with a simple
R, C lowpass filter (Figure 5). The cutoff frequency of the
output filter should be fCLK/3.
AGND (Pins 3, 5): For dual supply operation these pins
should be connected to a ground plane. For single supply
operation both pins should be tied to one half supply
(Figure 2).
V+, V– (Pins 4, 12): Should be bypassed with a 0.1F
capacitor to an adequate analog ground. Low noise,
nonswitching power supplies are recommended.
To avoid
latchup when the power supplies exhibit high turn-on
transients, a 1N5817 Schottky diode should be added
from the V+ and V– pins to ground (Figures 1 and 2).
INV A, R(h, I) (Pins 7, 14): A very short connection
between Pin 7 and Pin 14 is recommended. This connec-
tion should be preferably done under the IC package. In a
breadboard, use a one inch, or less, shielded coaxial cable;
the shield should be grounded. In a PC board, use a one
inch trace or less; surround the trace by a ground plane.
NC (Pin 8 ): Pin 8 is not internally connected, it should be
preferably grounded.
50/100 Ratio (Pin 10): For an fCLK/fC ratio of 50:1,
Pin 10 should be tied to V+. For an fCLK/f –3dB ratio of
100:1, Pin 10 should be tied to V–. When Pin 10 is at
midsupplies (i.e. ground), the filter response is neither
Cauer nor transitional. Table 6 illustrates this response.
Bypassing Pin 10 with a 0.1F capacitor reduces the
already small clock feedthrough.
(Pin Numbers Refer to the 14-Pin Package)
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